Data processing: design and analysis of circuit or semiconductor mask inventions 12/05

20050289484 - Externalization of coil structure patterns: A user can create a coil structure pattern on a display screen and annotate it with information such as comments, key values, and script fragments. Generating a coil structure pattern comprises receiving at least one pattern or sub-pattern, and assembling a layout comprising the pattern or sub-pattern. A parameter value,...

20050289485 - Hardware/software design tool and language specification mechanism enabling efficient technology retargeting and optimization: An innovative hardware/software design tool provides four modes of operation for converting an electronic design specification and zero or more technology specifications into realization of the electronic design in computer hardware, software and firmware. The first mode of operation compiles design and logic technology specifications into a model which can...

20050289486 - Equivalence checking of scan path flush operations: A method, apparatus, system, and signal-bearing medium that in an embodiment apply a latch behavior to a first and second netlist, where the latch behavior exhibits transparent behavior. Flush enabling conditions are applied to the first netlist and a second netlist. For each latch in a first scan chain in...

20050289490 - Integrated approach for design, simulation and verification of monolithic, silicon-based opto-electronic circuits: Computer-aided design (CAD) tools are used to perform the integrated design, verification and layout of electrical and optical components in a monolithic, silicon-based electro-optic chip. Separate top-level behavioral logic designs are prepared for the three different types of elements included within the final, silicon-based monolithic structure: (1) digital electronic integrated...

20050289487 - Method and system for dynamic modeling and recipe optimization of semiconductor etch processes: A method and system are disclosed for creating dynamic models of etch processes in semiconductor manufacturing. In one embodiment, a method comprises modeling an etch process used in semiconductor manufacturing to generate a dynamic process model. The dynamic process model is used to determine input values that result in a...

20050289489 - On-board performance monitor and power control system: A system and method for controlling performance and/or power based on monitored performance characteristics. Various aspects of the present invention may comprise an integrated circuit comprising a first circuit module that receives electrical power. A second circuit module may monitor one or more performance characteristics of the first circuit module...

20050289488 - System and method for mask defect detection: A mask defect detection system. The mask defect detection system comprises a first processing device, a second processing device, a third processing device, and a storage device. The first processing device processes mask design information to generate first writer-formatted mask information, wherein the first processing device comprises a first processing...

20050289491 - Method and computer program for estimating cell delay from a table with added voltage swing: A method and computer program for estimating a cell delay for an integrated circuit design include steps of: (a) selecting a range of values for cell ramptime and load; (b) selecting a range of values for an additional cell parameter; (c) arranging the values for cell ramptime, load, and the...

20050289492 - Method of lsi designing and a computer program for designing lsis: An LSI designing method using one or more functional blocks each containing two or more flip flops, includes the following: preparing a timing model which can be used under a first mode and a second mode; performing functional design of some functional elements each of which includes one or more...

20050289493 - Method and apparatus for designing a layout, and computer product: An apparatus for designing a layout includes an arranging unit that arranges, on a large-scale-integrated chip, a cell in which a signal line segment that is not connected to a terminal is formed; a wiring unit that wires a signal line to an arbitrary wiring layer of the large-scale-integrated chip;...

20050289495 - Graphical interface to layout processing components and connections: According to some embodiments, a graphical interface is provided to facilitate the layout of processing components and connections....

20050289494 - I/o circuit power routing system and method: A method (400) of determining widths (W) and/or routes of I/O power routes (112) between one or more power distribution networks (108) and a plurality of I/O circuits (104) based on IR drop, electromigration, and electrostatic discharge electrical requirements. The method includes initially routing the I/O power routes and then...

20050289496 - Symmetric signal distribution through abutment connection: The present invention provides a method and apparatus for managing a large number of associated interconnects within an integrated circuit involving a modular approach to the macro cell layout. In particular, internal signal paths are created within each macro cell that permit connections to other macros by abutting these macros...

20050289497 - Layout designing/characteristic analyzing apparatus for a wiring board: A layout designing/characteristic analyzing apparatus for a wiring board includes a module library memory for storing in advance for each of wiring board modules which are constituents of the wiring board, moduled circuit information on moduled circuits which constitute a wiring board circuit, wiring information and an analysis model for...

20050289499 - High level synthesis method for semiconductor integrated circuit: A CDFG which is a graph representing calculations and a data flow included in the design specifications of a circuit is generated S101, a clock cycle required for the processing is obtained and thus an allocated resource connection graph is generated S102. When the allocated resource connection graph includes nodes...

20050289498 - Processing and verifying retimed sequential elements in a circuit design: Provided are a method, system, and program for processing and verifying circuit designs. A circuit design specification written in a hardware definition language is received and zero delay black box code is added to the circuit design specification to position the zero delay black boxes at sequential elements. A synthesis...

20050289500 - Method for planning layout for lsi pattern, method for forming lsi pattern and method for generating mask data for lsi: First, multiple circuit patterns, which will eventually make an LSI, are designed on a cell-by-cell basis, and an initial placement is made for the circuit patterns designed. Next, optical proximity corrections are performed on at least two of the circuit patterns that have been initially placed to be adjacent to...

20050283743 - Method for generating hardware information: A method is provided that generates hardware information for executing a first program including a first algorithm that repeats a first process, the hardware information being suited to implementing a “for” loop written in C language in a device in which a plurality of PE are connected and a circuit...

20050283744 - Integrated circuit designing system, method and program: When a simulation model generation unit converts logic on the gate level into a basic primitive which can be executed by a simulator to generate a simulation model, for the basic primitives a degeneracy processing unit determines and deletes a gate which can be deleted and which will not affect...

20050283745 - Design checks for signal lines: Some embodiments provide identification of a first polyline and a second polyline associated with a differential signal, determination of whether a distance between a segment of the first polyline and a segment of the second polyline is within a first tolerance, determination, if the distance is not within the first...

20050283747 - Opc simulation model using socs decomposition of edge fragments: A system for estimating image intensity within a window area of a wafer using a SOCS decomposition to determine the horizontal and vertical edge fragments that correspond to objects within the window area. Results of the decomposition are used to access lookup tables that store data related to the contribution...

20050283746 - System and method for calculating trace lengths of a pcb layout: A system for calculating trace lengths of a PCB layout includes a computer (10) and a database (11). The computer includes: an object setting module (100) for setting objects to define section rules; a section rule defining module (101) for selecting objects as a start point and an end point...

20050283749 - Dynamic slew rate controlling method and device for reducing variance in simultaneous switching output: A dynamic slew rate controlling method and a device is provided to reduce SSO variance generated from voltage noises, which is as a result of a plurality of data bits switching to the same state simultaneously while the I/O bus transmits these data bits. The device and method at first...

20050283748 - Slack value setting method, slack value setting device, and recording medium recording a computer-readable slack value setting program: A slack value setting device comprises a worst path selecting section, a first slack value calculating section for calculating slack value set up to each of the transit pins on the worst path, a first slack value setting section for setting up the slack value to each of the transit...

20050283750 - Method and apparatus for designing a layout, and computer product: An arranging unit arranges a cell obtained from a net list input by an input unit on a large scale integration chip. A net extracting unit extracts an arbitrary net to be tested from a set of the cells arranged. An information extracting unit extracts, based on correlation information between...

20050278659 - Cell library providing transistor size information for automatic circuit design: A simple, approximate power optimization in connection with automatic large scale circuit design using a cell library is provided. The cell library of the present invention provides active region information for each cell, and preferably also provides conventional parameters such as cell physical area and cell performance information. Typically, several...

20050278658 - Standard cell library having cell drive strengths selected according to delay: A cell library which enables reduced quantization over-design in large scale circuit design is provided. Library cells having the same cell function have drive strengths selected to provide delays about equal to a predetermined set of design delays, at a nominal load corresponding to the cell function. In contrast, conventional...

20050278660 - Automatic circuit design method with a cell library providing transistor size information: A simple, approximate power optimization in connection with automatic large scale circuit design using a cell library is provided. The cell library of the present invention provides active region information for each cell, and preferably also provides conventional parameters such as cell physical area and cell performance information. Typically, several...

20050278661 - Multi-valued digital information retaining elements and memory devices: The invention discloses models and methods to create stable binary and non-binary sequential devices comprised of one or more logic functions of which an output signal is uniquely related to an input signal. Methods and apparatus for non-binary single independent input information retaining devices from two logic functions are disclosed....

20050278667 - Integrated circuit diagnosing method, system, and program product: The invention provides a method, system, and program product for diagnosing an integrated circuit. In particular, the invention captures one or more images for each relevant circuit layer of the integrated circuit. Based on the image(s), a component netlist is generated. Further, a logic netlist is generated by applying hierarchical...

20050278663 - Method and system for improving integrated circuit manufacturing productivity: A method and a system for improving manufacturing productivity of an integrated circuit. The method including: (a) generating a set of physical design rules, (b) assigning a rule scoring equation to each physical design rule of the set of physical design rules; (c) checking a physical design of the integrated...

20050278662 - Method for preventing circuit failures due to gate oxide leakage: A method is disclosed for preventing circuit failures due to gate oxide leakage, and is used to efficiently check many nets of a circuit on a chip or within a macro to find logical fails due to gate oxide leakage using DC calculations, wherein the gate leakage is treated as...

20050278665 - Methods to gather and display pin congestion statistics using graphical user interface: The present invention is a method for collecting, analyzing, and displaying statistics regarding block pin placement prior to routing of an integrated circuit. The statistics are graphically displayed in a graphical user interface (GUI). The GUI graphically displays indications of where block pin congestion problems lie, which allows an integrated...

20050278664 - Predicting power consumption for a chip: A method, an apparatus, and a computer program are provided for predicting power consumption for chip. The model for predicting power consumptions is modified so at to provide a high degree of accuracy with a minimal amount of computing time. Traditionally, when modeling a chip, a vast amount of time...

20050278666 - System and method for testing and configuring semiconductor functional circuits: The present invention systems and methods enable configuration of functional components in integrated circuits. A present invention system and method can flexibly change the operational characteristics of functional components in an integrated circuit die based upon a variety of factors including manufacturing defects, compatibility characteristics, performance requirements, and system health...

20050278669 - Invariant checking: In one embodiment, a method for invariant checking includes executing one or more first steps of a finite state machine (FSM) corresponding to one or more binary decision diagrams (BDDs) to traverse a state space of the FSM in a first direction with respect to an initial state and an...

20050278670 - Mechanical-electrical template based method and apparatus: A method and apparatus for identifying sections of an existing schematic that are consistent with best design practices, the method comprising the steps of providing a template set, each template specifying a sub-set of components and relationships that are consistent with best design practices and examining the existing schematic to...

20050278668 - Method of estimating crosstalk noise in lumped rlc coupled interconnects: A method for efficiently estimating crosstalk noise of high-speed VLSI interconnects is provided. In the invention, high-speed VLSI interconnects are modeled as lumped RLC coupled trees. The inductive crosstalk noise waveform can be accurately estimated in an efficient manner using the linear time moment computation technique in conjunction with the...

20050278672 - Lsi design method: An LSI design method according to the present invention is to estimate a timing uncertainty in an early stage of design for each item of which an influence on timing is uncertain among respective items requiring consideration relating to establishment of timing; and define a timing margin in each design...

20050278671 - Method and system for modeling variation of circuit parameters in delay calculation for timing analysis: A system, method, and computer program accurately models circuit parameter variation for delay calculation. For any given circuit parameter value, a cell is characterized at just three values in the circuit parameter range. An interpolation process generates an equation to calculate delay using the characterization data from the three circuit...

20050278675 - General purpose delay logic: A logic circuit for delaying a signal input thereto by a number of clock cycles X is described. In one embodiment, the logic circuit comprises a demultiplexer (“DEMUX”) which includes an input for receiving the signal and N outputs; a register array comprising at least X registers, wherein each of...

20050278674 - Nested design approach: A structure for a system of chip packages includes a master substrate and at least one subset substrate of the master substrate. The subset substrate includes a portion of the master substrate that has an identical pin out pattern as the portion of the master substrate. The subset substrate has...

20050278673 - Thin-film transistor circuit, design method for thin-film transistor, design program for thin-film transistor circuit, design program recording medium, design library database, and display device: A thin-film transistor circuit includes a crystallized semiconductor thin film two-dimensionally partitioned into crystal-grain-defining areas each of which accommodates a crystal grain larger than a predetermined size, thin-film transistors each of which has a channel region placed at the center position of a corresponding one of the crystal-grain-defining areas, and...

20050278676 - Method of physical planning voltage islands for asics and system-on-chip designs: Voltage islands enable a core-level power optimization of ASIC/SoC designs by utilizing a unique supply voltage for each cluster of the design. Creating voltage islands in a chip design for optimizing the overall power consumption consists of generating voltage island partitions, assigning voltage levels and floorplanning. The generation of voltage...

20050278677 - Novel test structure for automatic dynamic negative-bias temperature instability testing: The invention describes a novel test structure and process to create the structure for performing automatic dynamic stress testing of PMOS devices for Negative Bias Temperature Instability (NBTI). The invention consists of an integrated inverter, two integrated electronic switches for switching from stress mode to device DC characterization measurement mode,...

20050278678 - Substrate contact analysis: A method of analyzing substrate yield, where a substrate yield map and a substrate contact map are selected and overlaid to produce a composite map. First elements of the substrate yield map are compared to second elements of the substrate contact map to determine a degree of correlation between the...

20050278679 - Device for estimating number of board layers constituting board, system including the device, and method for estimating the same and program for executing the method: A device for estimating the required number of board layer to provide necessary wiring in a printed circuit board or a LSI package, a system including the device, a method and a program for estimating the same. In this system, positional information of pins mounted to each component and a...

20050278680 - Methodology for scheduling, partitioning and mapping computational tasks onto scalable, high performance, hybrid fpga networks: An automatically reconfigurable high performance FPGA system that includes a hybrid FPGA network and an automated scheduling, partitioning and mapping software tool adapted to configure the hybrid FPGA network in order to implement a functional task. The hybrid FPGA network includes a plurality of field programmable gate arrays, at least...

20050278681 - Method for synthesizing domino logic circuits: A method for synthesizing a domino logic circuit design from a source circuit definition using a static logic circuit synthesis tool includes generating a preliminary domino logic circuit design using the circuit synthesis tool and optimizing an attribute of the preliminary domino logic circuit design by substituting a static cell...

20050278682 - Determining hardware parameters specified when configurable ip is synthesized: An attribute of a hardware feature to be customized in a soft core is parameterized so that a value received from a user can be used to generate a description of a circuit containing the customized hardware feature. The generated description also describes, in accordance with the invention, a register...

20050278684 - Merging of infrastructure within a development environment: A development environment includes a graphical design tool and a build agent. The graphical design tool allows a designer to design a primary logic component of a circuit. The graphical design tool generates modules using a hardware description language to represent the primary logic component of the circuit. The modules...

20050278683 - Method, system and program product for specifying and using register entities to configure a simulated or physical digital system: In at least one hardware definition language (HDL) file, at least one design entity containing a functional portion of a digital system is specified. The design entity logically contains first and second latches each having a respective plurality of different possible latch values. With one or more statements, a first...

20050278685 - Matrix optical process correction: A method for performing a matrix-based verification technique such as optical process correction (OPC) that analyzes interactions between movement of a fragment on a mask and one or more edges to be created on a wafer. In one embodiment, each edge to be created is analyzed and one or more...

20050278686 - Fragmentation point and simulation site adjustment for resolution enhancement techniques: A method of performing a resolution enhancement technique such as OPC on an initial layout description involves fragmenting a polygon that represents a feature to be created into a number of edge fragments. One or more of the edge fragments is assigned an initial simulation site at which the image...

20050273731 - Operation-related information display method and operation-related information display system: An operation-related information display method includes storing information for identifying a printed-wiring board and information related to the printed-wiring board, identifying the printed-wiring board, obtaining information related to the printed-wiring board corresponding to the identified printed-wiring board, and when voluntary information is designated in the obtained information related to the...

20050273732 - Optimization and design method for configurable analog circuits and devices: Optimization design method for configurable analog circuits and devices resulting from same. An implementation fabric for a given application domain can be accurately pre-characterized in terms of devices and parasitics. Customization structures are designed and characterized to be applied to the fabric to customize a device for a particular application....

20050273734 - Correcting design data for manufacture: A method of correction for design data includes the steps of sequentially applying a plurality of corrections to a plurality of features based on a plurality of feature tolerances to design data in a predetermined order, and providing corrected design data....

20050273738 - Guided capture, creation, and seamless integration with scalable complexity of a clock specification into a design flow of an integrated circuit: A clock integration method, tool, and a computer program product that captures, creates, and seamlessly integrates a clock specification to achieve a correct-by-construction design flow of a semiconductor product, such as an ASIC, from a partially manufactured semiconductor platform. The clocking elements of the design flow are combined and displayed...

20050273737 - Language and templates for use in the design of semiconductor products: During the design of semiconductor products which incorporates a user specification and an application set, the application set being a partially manufactured semiconductor platform and its resources, a template engine is disclosed which uses a simplified computer language having a character whereby data used in commands identified by the character...

20050273733 - Opc conflict identification and edge priority system: An integrated circuit verification system provides an indication of conflicts between an OPC suggested correction and a manufacturing rule. The indication specifies which edges segments are in conflict so that a user may remove the conflict to achieve a better OPC result. In another embodiment of the invention, edge segments...

20050273739 - Pattern analysis method, pattern analysis apparatus, yield calculation method and yield calculation apparatus: A critical area of one via is calculated on the basis of sizes of a plurality of vias, sizes of defects causing random defect failures of the plural vias and a distance from the one via to another adjacent via....

20050273736 - Rules and directives for validating correct data used in the design of semiconductor products: A method, rules and directives engine, and a computer program product that simplifies the design of semiconductor products. Starting with an application set which is a partially manufactured semiconductor platform that is correct-by-construction, as a chip designer inserts her/his own designs into the platform, a system of rules and directives...

20050273735 - Tuple propagator and its use in analysis of mixed clock domain designs: Names of signals are propagated through a circuit design inside tuples, with each tuple including at least a signal name and a sequential depth. A tuple being propagated is added to a list of zero or more tuples currently identified with a circuit element, unless a tuple of the same...

20050273740 - Program, method and apparatus for analyzing transmission signals: From design information on a circuit board a wiring designation unit designates a wiring model for signal analysis. A first analysis unit generates, through a 3-D electromagnetic analysis, a first output waveform received at a receiving end of a wiring model when a first input signal pattern changing from 0...

20050273742 - Integrated circuit with dynamically controlled voltage supply: An electronic system (10). The system comprises circuitry (P1) for receiving a system voltage from a voltage supply. The system also comprises circuitry (141), responsive to the system voltage, for providing data processing functionality. The circuitry for providing data processing functionality comprises a critical path (CP1) and the critical path...

20050273741 - Method and computer program for management of synchronous and asynchronous clock domain crossing in integrated circuit design: A method and computer program are disclosed for managing synchronous and asynchronous clock domain crossings that include steps of: (a) receiving as input an integrated circuit design; (b) identifying paths between synchronous clock domains and paths between asynchronous clock domains in the integrated circuit design; and (c) if a path...

20050273744 - Ic tiling pattern method, ic so formed and analysis method: The invention provides a method for providing an integrated circuit (6) having a substantially uniform density between parts (10, 12, 14 and 16) of the IC that are non-orthogonally angled. In particular, the invention provides fill tiling patterns (32, 34) oriented substantially parallel to electrical structure regardless of their angle....

20050273743 - Net/wiring selection method, net selection method, wiring selection method, and delay improvement method: The present invention relates to a net/wiring selection method for selecting, from among nets/wirings wired on the basis of layout information, a net/wiring whose layout is to be changed with priority in order to improve a delay. To enable efficient elimination of a critical path, the method is arranged to...

20050273745 - Determining feasibility of ic edits: A computer method of analyzing an integrated circuit (“IC”) masked design data, comprising grouping into a cluster areas of layers preceding a target metal layer that are suitable for milling, deleting portions of the target metal layer that do not meet minimum tool spacing requirements to produce a modified metal...

20050273747 - Local preferred direction routing: Some embodiments of the invention provide a method for routing. The method defines at least one wiring layer that has at least two regions with different local preferred wiring directions. The method then uses the differing local preferred wiring directions to define a global route on the wiring layer. The...

20050273746 - Method and apparatus for generating layout regions with local preferred directions: Some embodiments of the invention provide a method for defining wiring directions in a design layout having several wiring layers. The method decomposes a first wiring layer into several non-overlapping regions. It assigns at least two different local preferred wiring directions to at least two of the regions. In some...

20050273748 - Local preferred direction routing: Some embodiments of the invention provide a method for defining routes in a design layout. The method defines at least one particular wiring layer that has at least two regions with different local preferred wiring directions. The method then uses the differing local preferred wiring directions to define a detailed...

20050273749 - Structured asic device with configurable die size and selectable embedded functions: One embodiment of the present invention provides for a master or universal base and base tooling which addresses the general purpose Structured ASIC requirements. Another embodiment of the present invention provides for a common set of base tooling from which the master/universal base is created as well as additional custom...

20050273750 - Turn architecture for routing resources in a field programmable gate array: A turning structure for routing channels in a field programmable gate array, comprising a first plurality of routing channels having a first direction and a second plurality of routing channels having a second direction. The first plurality of routing channels intersects the second plurality of routing channels to form a...

20050273751 - Method of generating multiple hardware description language configurations for a phase locked loop from a single genetic model for integrated circuit design: A method and computer program are disclosed for generating a hardware description language configuration from a generic phase locked loop architecture that include steps of: (a) receiving as input values for a set of configuration variables for a phase locked loop; (b) applying the values for the set of configuration...

20050273752 - Optimization of memory accesses in a circuit design: Methods and apparatus for optimizing memory accesses in a circuit design are described. According to one embodiment, a method comprises identifying a subset of variables from a multi-variable memory space that are accessed by a plurality of loops, storing the subset of variables in a separately accessible memory space, and...

20050273753 - Method and system for designing manufacturable patterns that account for the pattern- and position-dependent nature of patterning processes: Computational models of a patterning process are described. Any one of these computational models can be implemented as computer-readable program code embodied in computer-readable media. The embodiments described herein explain techniques that can be used to adjust parameters of these models according to measurements, as well as how predictions made...

20050273754 - Pattern data correction method, pattern checking method, pattern check program, photo mask producing method, and semiconductor device manufacturing method: A pattern data correction method is disclosed, which comprises preparing an integrated circuit pattern, setting a tolerance to the pattern that is allowable error range when the pattern is transferred on a substrate, creating a target pattern within the tolerance, and making correction for the target pattern to make a...

20050268256 - Modeling resolution enhancement processes in integrated circuit fabrication: A Wafer Image Modeling and Prediction System (“WIMAPS”) is described that includes systems and methods that generate and/or apply models of resolution enhancement techniques (“RET”) and printing processes in integrated circuit (“IC”) fabrication. The WIMAPS provides efficient processes for use by designers in predicting the RET and wafer printing process...

20050268258 - Rule-based design consultant and method for integrated circuit design: A rule-based design consultant and analysis method for an integrated circuit (“IC”) layout design compares an IC design against a list of rules. The IC design information may be included in a set of databases, including a database containing physical implementation and technology specific timing and area information. The consultant...

20050268257 - Semiconductor integrated circuit, method for designing semiconductor integrated circuit and system for designing semiconductor integrated circuit: The semiconductor integrated circuit capable of reducing an interconnection width as compared with conventional one while suppressing electromigration effectively. An input unit 101 stores interconnection information in an interconnection information storage unit 104. An arithmetic operation unit 102 acquires the interconnection information upon accessing the interconnection information storage unit 104...

20050268260 - Capacitance measurements for an integrated circuit: A method and apparatus for determining capacitance of wires in an integrated circuit is described. The capacitance information derived according to the invention can be used, for example, to calibrate a parasitic extraction engine or to calibrate an integrated circuit fabrication process. The capacitance information can also be used for...

20050268261 - Circuit analyzing method and circuit analyzing device: A circuit analyzing device according to the present invention comprises a capacitance value extracting unit for extracting a capacitance value of a functional element from design information including layout information of a semiconductor integrated circuit and a capacitance value outputting unit for displaying the functional element in the semiconductor integrated...

20050268262 - System and method for calculating effective capacitance for timing analysis: A method involves: accessing data representing an interconnect model, where the interconnect model includes a driving point node and is not a lumped capacitance model; calculating a value of an effective capacitance of the interconnect model to be inversely proportional to a voltage at the driving point node of the...

20050268259 - System and method for verifying trace widths of a pcb layout: A method for verifying trace widths of a printed circuit board (PCB) layout includes the steps of: loading a PCB layout document from a database; defining a verifying area for a PCB layout specified in the PCB layout document; receiving preset design rules; creating a data structure, and loading information...

20050268264 - Apparatus and method for calculating crosstalk: In a crosstalk calculating method, a basic noise amplitude signal applied to a victim net is determined in a basic noise generation period specified based on a voltage signal transferred on an aggressor net in a semiconductor circuit. First and second signal portions applied to the victim net in first...

20050268265 - Metastability effects simulation for a circuit description: A circuit design that contains at least two clock domains is simulated using a novel system and method for injecting the effects of metastability. The system includes detectors for detecting, during simulation, when a clock in a transmit clock domain and a clock in a receive clock domain are aligned...

20050268266 - Method and apparatus for analyzing post-layout timing violations: A tool for analyzing timing violations reports is presented herein. The tool comprises a script which parses a log file containing any number of timing violation reports from a simulation of a layout design. The tool filters, consolidates, and sorts the timing violations and presents the foregoing in a report...

20050268263 - Method and apparatus for fixing hold time violations in a circuit design: To fix hold time violations, timing analysis is initially performed on a circuit design for each set of timing constraints to determine a setup slack and a hold slack for each signal path for that set of timing constraints. The slack for a signal path indicates the amount of timing...

20050268267 - Methods and systems for mixed-mode physical synthesis in electronic design automation: Methods and systems for electronic design automation includes clustering objects into more manageable numbers of objects. Clustering is optionally performed to reduce or minimize interconnections between clusters. Clustering optionally includes multi-level clustering. The clusters, and any unclustered objects, are floorplanned. Floorplanning positions the clusters so as to reduce or minimize...

20050268268 - Methods and systems for structured asic electronic design automation: Electronic design automation (“EDA) methods and systems for structured ASICs include accessing or receiving objects representative of source code for a structured ASIC. The objects are flattened to remove hierarchies associated with the source code, such as functional RTL hierarchies. The flattened objects are clustered to accommodate design constraints associated...

20050268270 - Layout data saving method, layout data converting device and graphic verifying device: There are saved layout data which have parent cell information indicative of higher order cell data to directly refer to low order cell data (or basic element data), thereby defining a reverse hierarchical structure. More specifically, both of basic element data (figD1 and figD2) have cell data (cell2) as the...

20050268269 - Methods and systems for cross-probing in integrated circuit design: When designing integrated circuits, RTL source code is received and converted into objects. Objects may include a reference to relevant lines of source RTL code. A graphical user interface (“GUI”) displays the RTL code in an RTL window. The GUI also displays one or more representations of the objects in...

20050268271 - Loop manipulation in a behavioral synthesis tool: Methods and apparatus for analyzing and processing loops within an integrated circuit design are described. According to one embodiment, the processing comprises unrolling loops. In another embodiment, the processing comprises pipelining loops. In yet another embodiment, the processing comprises merging loops. In any of the disclosed embodiments, loops comprise independent...

20050268272 - Method and apparatus for optimizing fragmentation of boundaries for optical proximity correction (opc) purposes: The present invention is directed to a method and apparatus for optimizing fragmentation of integrated circuit boundaries for optical proximity correction (OPC) purposes. The present invention may balance the number of vertices and the “flexibility” of the boundary and may recover fragmentation according to the process intensity profile along the...