Data processing: design and analysis of circuit or semiconductor mask inventions 11/05

20050262458 - Capacitance modeling: Methods, systems and apparatus for modeling capacitance for a structure comprising a pair of long conductors surrounded by a dielectric material and supported by a substrate. In particular, the structure may be on-chip coplanar transmission lines over a conductive substrate operated at very high frequencies, such that the substrate behaves...

20050262457 - Checking the robustness of a model of a physical system: The invention provides a system and a method for verifying the robustness of a model of a physical system, the method comprising the following steps: defining a first model of the physical system comprising a set of components and at least one input interface for inserting input values, said first...

20050262454 - Method for vlsi system debug and timing analysis: A method for characterizing circuit activity in an IC. Generally, the method comprises the steps of activating an IC, resolving the switching activity in space and time, and generating a representation of the switching behavior which differentiates the time that circuits or transistors switch. One embodiment of the invention, utilizes...

20050262455 - System and method for verifying a layout of circuit traces on a motherboard: A system for verifying a layout of circuit traces on a motherboard includes a computer (1) and a database (2). The database is used for storing data generated and used by the system. The computer includes: a substandard layout area creating module (101) for creating substandard layout areas; a substandard...

20050262456 - Verifying one or more properties of a design using sat-based bmc: In one embodiment, a method for satisfiability (SAT)-based bounded model checking (BMC) includes isolating information learned from a first iteration of an SAT-based BMC process and applying the isolated information from the first iteration of the SAT-based BMC process to a second iteration of the SAT-based BMC process subsequent to...

20050262459 - Automatic tuning of signal timing: A system and method for automatically tuning timing of a signal (e.g., a data timing signal) utilizing determined delay of a variable delay element and for utilizing such a tuned signal. Various aspects of the invention may comprise experimentally determining delay characteristics of an on-chip variable delay circuit utilizing an...

20050262460 - Method for creating a jtag tap controller in a slice for use during custom instance creation to avoid the need of a boundary scan synthesis tool: A method and system is provided for creating a tap controller in a slice for use during custom instance creation to avoid the need of a boundary scan synthesis tool. Aspects of the present invention include during slice creation, using a software tool to create a test access port (TAP)...

20050262461 - Input/output circuits with programmable option and related method: A chip with programmable input/output (I/O) circuits has a plurality of layout layers including a plurality of same layouts in a plurality of positions of the layout layers so as to implement a plurality of sub-circuit cells with the same layout, and at least a connection layer having different layouts...

20050262462 - Method and apparatus for designing multi-tier systems: A system and method for selecting a preferred design for a multi-tiered architecture of components based on a set of established criteria is provided. The system and method receive a model describing different design constructions and a set of performance and availability requirements and produces a design or set of...

20050262463 - Wiring optimizations for power: An electrical wiring structure and method of designing thereof. The method identifies at least one wire pair having a first wire and a second wire. The second wire is already tri-stated or can be tri-stated. The wire pair may have a same-direction switching probability per clock cycle that is no...

20050262464 - Integrated circuit routing resource optimization algorithm for random port ordering: A method of routing an integrated circuit signal bus is provided. One of a set of blocks having ports that are to be connected to the signal bus is selected as a primary block, the ports of which are positioned so that no two ports of that block lie within...

20050262465 - Handling of unused coreware with embedded boundary scan chains to avoid the need of a boundary scan synthesis tool during custom instance creation: A method and system is provided for handling unused structures in a slice during custom instance creation to avoid the need of a boundary scan synthesis tool, wherein the slice includes an embedded boundary scan chain having a particular length and order. Aspects of the present invention include using a...

20050262468 - Designing method and device for phase shift mask: The work load spent on designing a trench-type, Levenson-type phase shift mask is lightened and the working time for the designing process is shortened. A pattern 11, having a plurality of apertures, is designed by means of a designing tool 10. In a database 30 are prepared optimal functions that...

20050262467 - Method and system for utilizing an isofocal contour to perform optical and process corrections: A method and system for performing optical proximity correction (OPC) on an integrated circuit (IC) mask design is disclosed. The system and method of the present invention includes identifying a first feature in the mask design, generating an isofocal contour for the identified feature, and utilizing the isofocal contour to...

20050262466 - Method for modifying design data for the production of a component and corresponding units: A method is described in which design data are prescribed which stipulate a geometrical design for a component. The design is used to produce an altered geometrical design, for example through relocations in a region. For the two designs, assessment criteria are ascertained and compared. Depending on the comparison result,...

20050262469 - Method of calculating predictive shape of wiring structure, calculating apparatus, and computer-readable recording medium: In a calculating apparatus for calculating a predictive shape of a wire structure using a finite element model, a predictive shape of the finite element model which is in a physically balanced condition based on physical properties and restriction conditions is calculated. When it is determined that the predictive shape...

20050257177 - System on chip development with reconfigurable multi-project wafer technology: A method is disclosed for designing a semiconductor circuit on a multi-project wafer (MPW). One or more standard modules designed by one or more vendors with verified functions are first identified. Some of the standard modules are charged based on usage. At least one reconfigurable module of the MPW is...

20050257178 - Method and apparatus for designing electronic circuits: Methods and apparatus for designing electronic circuits, including analog and mixed signal circuits. In one exemplary embodiment, a hierarchical design and sizing flow is used, in conjunction with one or more evaluation models (e.g., performance and feasibility models), such that results generated at one level remain valid and pertinent other...

20050257180 - Method of optimizing rtl code for multiplex structures: A method and computer program are disclosed for optimizing RTL code for an integrated circuit design that include steps of: (a) receiving as input a first register transfer level code for an integrated circuit design; (b) receiving as input a user defined optimum multiplex structure; (c) analyzing the first register...

20050257179 - Method, system and program product for building an automated datapath system generating tool: A method, system and program product for building an automated bit-sliced datapath system generating tool so design can be performed at a higher level, and automated generation of the synthesizable HDL representation can be accomplished are disclosed. A method defines datapath system characteristics, defines core/pin rules, and then constructs class-type...

20050257181 - Method and apparatus for identifying line-end features for lithography verification: One embodiment of the invention provides a system that facilitates identifying line-end features in a layout for an integrated circuit. The system operates by first receiving the layout for the integrated circuit. Next, the system selects a polygon from the layout and marks a line-end seed on the polygon. The...

20050257182 - System and method for verifying trace distances of a pcb layout: A system for verifying trace distances of a PCB layout includes a computer (10) and a database (11). The computer includes: a segment receiving module (100) for receiving segments of a selected trace, and depositing the segments in a segment set; a segment selecting module (101) for selecting an unverified...

20050257183 - Method for generating a command file of a group of drc rules and/or a command file of a group of lvs/lpe rules: A method is capable of generating a command file of a group of design rule check (DRC) rules or layout versus schematic (LVS) rules and layout parasitic extraction (LPE) rules that can be used by a layout verification tool to verify the layout and the parasitic characteristics of an integrated...

20050257184 - Net list creating method, net list creating device, and computer program thereof: It is intended to provide net list creating method, net list creating device, and computer program thereof capable of creating net list of memory space by selecting optimum combination of memory macros and providing a control circuit for controlling and making the combination accessible as memory space from a previously...

20050257185 - Methods and apparatuses for validating ac i/o loopback tests using delay modeling in rtl simulation: Embodiments of the invention provide a logic simulation having a controllable delay model implemented therein that may be used to validate AC I/O loopback design in a pre-silicon environment by introducing delay models that allow the logic simulators to simulate analog behavior. For one embodiment of the invention, a fixed...

20050257186 - Operation system for programmable hardware: The proposed software-controlled FPGA system and method provides an operating system which controls partial reconfiguration of hardware logic blocks having equivalent properties as a standard software operating system. Said hardware control operating system enables to adjust compatible hardware logic blocks according to current running applications and attached hardware devices. The...

20050257187 - Fast and accurate optical proximity correction engine for incorporating long range flare effects: A method is described for performing model-based optical proximity corrections on a mask layout used in an optical lithography process having a plurality of mask shapes. Model-based optical proximity correction is performed by computing the image intensity on selected evaluation points on the mask layout. The image intensity to be...

20050257188 - Pattern correcting method, mask making method, method of manufacturing semiconductor device, pattern correction system, and computer-readable recording medium having pattern correction program recorded therein: There is disclosed a pattern correcting method comprising extracting a correction pattern, at least the one or more correction patterns being included in a first design pattern formed on a substrate, acquiring layout information from the first design pattern, the layout information affecting a finished plane shape of the correction...

20050257189 - Phase-shift lithography mapping method and apparatus: For phase-shifting micro lithography, a method of assigning phase to a set of shifter polygons in a mask layer separated by a set of target features includes assigning a first phase to a first shifter polygon, identifying a set of target features that touch the first shifter polygon, and assigning...

20050251761 - Integrated circuit configuration system and method: The present invention systems and methods enable configuration of functional components in integrated circuits. A present invention system and method can flexibly change the operational characteristics of functional components in an integrated circuit die based upon a variety of factors. In one embodiment, manufacturing yields, compatibility characteristics, performance requirements, and...

20050251762 - Methods and apparatus for synthesizable pipeline control: An organization and method of designing a processor of an integrated circuit are provided which includes identifying reusable portions of a custom design to be created for a processor. The processor is custom designed to meet specific performance criteria. Such custom designing includes custom designing macros for the reusable portions,...

20050251764 - Method of generating protected standard delay format file: A method of generating a protected standard delay format (SDF) file is disclosed. The interconnect delay descriptions of a SDF file are backwardly or forwardly integrated into the related cell delay descriptions according to their interconnection type to generate the protected SDF file. The total delay value of each signal...

20050251763 - Methods and apparatus for scan insertion: The traditional method of scan insertion and balancing clocks involves first having a system clock, which can be used for scan mode and normal mode, then synthesizing the design, defining scan chain or scan chains, and inserting them in the design using a script. After that, the cells are placed...

20050251766 - Circuit design interface: According to an example embodiment of an approach to circuit design processing involves using an interface for retrieving and processing circuit design data for use by a plurality of simulation tools. The interface includes an application program callable function configured to return functional classification data in response to an application...

20050251765 - Design verification of highly optimized synchronous pipelines via random simulation driven by critical resource scheduling: Testing a model of a logic circuit model. The testing includes generating valid random input stimulus sequences for a logic circuit model. Enumerating critical resource requirements, enumerating critical resource availabilities does this, and selecting of stimulus sequences and determining legal times for execution of said stimulus sequences based on resource...

20050251768 - Function verification method: A function verification method comprises preparing a first function block that can execute the required functions in a semiconductor integrated circuit, preparing a second function block to be a verification target having a substantially identical configuration as the first function block and verifying functions of the second function block using...

20050251767 - Processing of circuit design data: One example embodiment of an approach to circuit design analysis comprises partitioning a circuit design into first, second and boundary parts, the boundary part including circuit portions from each of the first part and second part at a boundary between the first part and second part. The first, second and...

20050251771 - Integrated circuit layout design methodology with process variation bands: A system for analyzing IC layouts and designs by calculating variations of a number of objects to be created on a semiconductor wafer as a result of different process conditions. The variations are analyzed to determine individual feature failures or to rank layout designs by their susceptibility to process variations....

20050251770 - System and method for determining signal coupling coefficients for lines: Various embodiments of a system, apparatus and method for determining the signal coupling coefficient of a line in the design of a substrate are disclosed. One apparatus embodiment comprises a line signal coupling coefficient tool....

20050251769 - System and method for determining signal coupling in a circuit design: Various embodiments of a system, apparatus and method for determining the signal coupling coefficient of a path in the design of a substrate are disclosed. One apparatus embodiment comprises a path signal coupling coefficient tool....

20050251772 - Assuring correct data entry to generate shells for a semiconductor platform: A method, system, and a computer program product to provide correct and complete input into a shell generation tool that provides the infrastructure for design and development of an integrated circuit. Given a definition of a platform, in part a partially manufactured semiconductor product having some diffused and some configurable...

20050251773 - Method and program product for modelling behavior of asynchronous clocks in a system having multiple clocks: Method and program product for analyzing an asynchronously clocked system. The system being analyzed has independently clocked subsystems with clock boundaries therebetween. The model identifies a boundary between the two independently clocked subsystems, and identifies behavior at the boundary between the two independently clocked subsystems. and modeling a latch at...

20050251774 - Circuit design property storage and manipulation: One example embodiment of property data storage includes using row and column names to identify properties to a particular circuit design component. Each of a plurality of columns in a relational database table is named with a property name indicative of a respective one of a plurality of circuit design...

20050251775 - Rotary clock synchronous fabric: Methods for generating a design for logic circuitry using rotary traveling wave oscillators (RTWOs) are described. A plurality of RTWOs are is arranged into an array of rows and columns. Adjacent elements in the array are interconnected so that the clocks in adjacent element are phase synchronous. Clocked devices are...

20050251776 - Integrated circuit design system: An integrated circuit design system has a second interface for displaying a plurality of description instructions corresponding to a specific integrated circuit according to a variety of display instructions, a first interface for inputting the display instructions and for updating a description instruction displayed on the second interface according to...

20050251777 - Method and structure for implementing enhanced electronic packaging and pcb layout with diagonal vias: A method and structure are provided for implementing enhanced electronic packaging and printed circuit board (PCB) layout. A diagonal via is formed at a selected angle between a first side and an opposite second side of a printed circuit board at a selected printed circuit board location. The diagonal via...

20050251778 - System and method for dynamically executing a function in a programmable logic array: A reconfigurable logic array (RLA) system (104) that includes an RLA (108) and a programmer (112) for reprogramming the RLA on a cyclical basis. A function (F) requiring a larger amount of logic than contained in the RLA is partitioned into multiple functional blocks (FB 1, FB2, FB3). The programmer...

20050251780 - Method for generating timing constraints of logic circuit: In hierarchical design of a logic circuit by utilizing lower-level blocks of the logic circuit, data on the logic circuit with the hierarchical structure, library data holding primitive information on the logic circuit and timing constraints on the lower-level blocks are input at a data input step. Based on these...

20050251779 - Modeling metastability in circuit design: A computer program (100, 200) encoded in a computer-programmable medium, and for causing a computer to perform circuit design. The code causes the computer to perform a set of steps. The steps comprise describing a first set of circuitry and describing a second set of circuitry. The steps also comprise...

20050251781 - Design pattern correcting method, design pattern forming method, process proximity effect correcting method, semiconductor device and design pattern correcting program: A design pattern correcting method of correcting a design pattern in relation to a minute step of the design pattern, is disclosed, which comprises extracting at least one of two edges extended from a vertex of the design pattern, measuring a length of the extracted edge, determining whether or not...

20050246667 - Bus structure, database and method of designing interface: With respect to each application, libraries, corresponding to operation models, for describing operations respectively attained by employing a Neumann CPU (bus structure), a Harvard CPU (bus structure) and a direction separate type CPU (bus structure) are registered. In a performance table of each library, the performance index of the library...

20050246668 - Method and device for an equivalence comparison of digital circuits: Assignment information items for assigning signal-path identifiers of circuit descriptions in accordance with a second description format also as a function of the circuit description in accordance with a first description format, from which circuit description the circuit descriptions in accordance with the second description format have been produced by...

20050246669 - Apparatus for and method of analyzing transmission characteristics of a circuit apparatus: A method of analyzing transmission characteristics of signal wiring in a circuit apparatus including the signal wiring and insulative layer is disclosed. The transmission characteristics are analyzed by dividing the circuit apparatus with a mesh and applying electromagnetic analysis method to each unit of the mesh. The method includes the...

20050246672 - Differential trace pair coupling verification tool: A method for verifying coupling in a differential trace pair group includes reading victim properties of a victim differential trace pair and culprit properties of a plurality of culprit differential trace pairs from a circuit design database. The method also includes calculating a plurality of coupling factors based on the...

20050246670 - Differential via pair coupling verification tool: A method for verifying coupling in a differential via pair group includes identifying a differential via pair group in a design database and identifying a victim differential via pair in the differential via pair group. All other differential via pairs in the differential via pair group are identified as culprit...

20050246671 - Method and apparatus for determining worst case coupling within a differential pair group: A method for calculating worst case coupling for a differential pair group includes identifying a victim differential pair and at least one culprit differential pair in the differential pair group, calculating a coupling factor between each of the culprit differential pairs and the victim differential pair, and summing the absolute...

20050246673 - Method and system for performing static timing analysis on digital electronic circuits: A method for performing static timing analysis on digital electronic circuits is disclosed. A snip (or DC adjust) file is initially generated. Static timing analysis is then performed on the final circuit netlist using the snip file. If the final circuit netlist meets all the timing constraints, the snip file...

20050246674 - Method and apparatus for designing integrated circuit layouts: A method for modifying an IC layout using a library of pretabulated models, each model containing an environment with a feature, one or more geometries, and a modification to the feature that us calculated to produce a satisfactory feature on a wafer. The model may also contain a simulation of...

20050246675 - Method and apparatus for designing integrated circuit layouts: A method for modifying an upper layout for an upper layer of an IC using information of a lower layout for a lower layer of the IC, the method including 1) receiving the upper layout containing features and modifications to features, 2) producing a density map of the lower layout...

20050246676 - Routing analysis method, logic synthesis method and circuit partitioning method for integrated circuit: The present invention relates to a routing analysis method for performing a routing analysis on an integrated circuit from a netlist which is information on a plurality of cells constituting the integrated circuit and routes connecting the cells, and the routing analysis method comprises a step (Step 1) of obtaining...