| Data-dependent jitter pre-emphasis for high-speed serial link transmitters -> Monitor Keywords |
|
|
 
Data-dependent jitter pre-emphasis for high-speed serial link transmittersRelated Patent Categories: Pulse Or Digital Communications, EqualizersData-dependent jitter pre-emphasis for high-speed serial link transmitters description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070177663, Data-dependent jitter pre-emphasis for high-speed serial link transmitters. Brief Patent Description - Full Patent Description - Patent Application Claims
FIELD OF THE INVENTION [0001] The present invention relates generally to data equalization techniques for high speed serial links. BACKGROUND OF THE INVENTION [0002] High bandwidth chip-to-chip interconnection is a crucial part of many systems today. High speed inputs/outputs (I/Os) are extensively used in server processors, memory-central processing unit (CPU) interfaces, multiprocessor systems, and gaming applications. With increasing speed of on-chip data processing, there is an increasing demand for higher data rates. These high speed I/Os must also be capable of supporting low cost package and board technologies which introduce large signal degradation through bandwidth loss, reflection, and crosstalk. [0003] Equalization of high-speed serial links has evolved to compensate inter-symbol interference (ISI) caused by frequency-dependent attenuation found in interconnects. Pre-emphasis-based equalization in the transmitter and decision feedback equalization in the receiver figure prominently in overcoming signal degradation and improving Bit Error Rate (BER). Currently, one challenge of equalization is minimizing power consumption while still improving signal integrity in the presence of attenuation and reflections. [0004] Transmitters are a significant portion of the serial link power budget. The transmitter is required to drive enough power over lossy interconnects to meet minimum receiver sensitivity requirements. The use of amplitude pre-emphasis techniques, such as feed forward equalization, increases the power consumption and chip area and places additional demands on the dynamic range of the transmitter. Also, in a transmission system with high cross-talk between the channels, especially the near end cross talk where a transmitter is leaking into a neighboring receiver, amplitude pre-emphasis will enhance the high frequency cross-talk of the victim receiver which implies that its signal to noise ratio will be degraded. [0005] In view of the foregoing, a growing need has been recognized in connection with improving upon the shortcomings and disadvantages presented by conventional arrangements. SUMMARY OF THE INVENTION [0006] In accordance with at least one presently preferred embodiment of the invention, there is broadly contemplated an expansion of the notion of pre-emphasis beyond conventional amplitude compensation of ISI, whereby phase pre-emphasis for compensating data-dependent jitter (DDJ) is introduced. DDJ can be addressed by exploiting the relationship between the data sequence and the timing deviation. Phase pre-emphasis improves the signal integrity with little additional power consumption in the transmitter and with no cross-talk penalty. [0007] In summary, one aspect of the invention provides an apparatus for providing data dependent jitter in data transmission, the apparatus comprising: an input arrangement for accepting data input; an arrangement for detecting and decoding transitions in the data input; the arrangement for detecting and decoding being adapted to ascertain data transition history in the data input; and an arrangement for applying at least one delay to at least a portion of the data input, based on the ascertained data transition history. [0008] Another aspect of the invention provides a method of providing data dependent jitter in data transmission, the method comprising the steps of: accepting data input; detecting and decoding transitions in the data input; the step of detecting and decoding comprising ascertaining data transition history in the data input; and applying at least one delay to at least a portion of the data input, based on the ascertained data transition history. [0009] For a better understanding of the present invention, together with other and further features and advantages thereof, reference is made to the following description, taken in conjunction with the accompanying drawings, and the scope of the invention will be pointed out in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS [0010] FIG. 1 is a block diagram of a first embodiment. [0011] FIG. 2 is a schematic illustration of channel effect on data-dependent jitter. [0012] FIG. 3 is a block diagram of a second embodiment. DESCRIPTION OF THE PREFERRED EMBODIMENTS [0013] Generally speaking, in a link where losses due to signal attenuation are dominating other channel impairments such as reflection due to discontinuities, the amount of DDJ of a random bit sequence at the end of a link, which corresponds to timing deviation from ideal transition time, depends on the previous bit sequences only. Thus, the amount of DDJ at a given transition time corresponding to a given channel can be predicted by simply keeping track of the previous transitions. Also, it can be shown that the most recent transitions in previous data bits contribute to DDJ with larger amount. Thus, most of the DDJ can be predicted and compensated for by only detecting some of the most recent transitions. For typical links, one needs to detect down to the three previous data transitions to predict most of the DDJ occurring at a the current data transition. [0014] Phase pre-emphasis manipulates the data transitions to neutralize DDJ at the end of the transmission channel. The delay of the data transition to be transmitted is dynamically changed depending on the previous bit sequence detected. In general, the highest frequency components of the data sequence are delayed before being transmitted in such a way that the arrival time of the different frequency components of the data sequence closely coincide at the end of the link. This delay (or phase) pre-distortion will thus increase both the timing and voltage margins of the signal at the end of the link. [0015] In accordance with one preferred embodiment of the present invention, a full-rate clock transmitter architecture approach shows how a serial type phase pre-distortion is implemented. In accordance with a second preferred embodiment of the present invention, a quarter-clock transmitter architecture shows how a parallel type phase pre-distortion is implemented. [0016] FIG. 1 illustrates the aforementioned first embodiment, corresponding to the front-end of a transmitter which performs phase pre-distortion on the serial data that is transmitted over the transmission medium possibly using a line driver. As shown, there are preferably provided single data bit time delay elements 102, 103 and 104, XOR gates 105, 106 and 107, a transition decoder 108 connected to outputs of XOR gates 105/106/107, programmable tap weights 109 and a programmable delay line 110. [0017] Preferably, a serial data stream 101 is successively delayed by the single data bit delay elements 102, 103 and 104. Though only three delay elements are shown, the actual number of these delay elements can be as high as needed depending how many previous transitions need to be detected in order to compute the pre-distortion delay to be applied to the current bit. XOR gate 105 compares signal 101 to the output of 102 to detect if a transition is occurring on the current bit to be transmitted. If a transition is present the output of XOR gate 105 will be high. XOR gates 106, 107 function similarly to gate 105 but, respectively, compare signal outputs from delay elements 102/103 and from 103/104. As with gate 105, if a transition is detected then the output of gate 106 or 107 will be high, as appropriate. Then, depending on the data transition history that is determined by the transition decoder 108, a pre-distortion delay is added or subtracted to the current data transition time using the programmable delay line 110. [0018] The amount of pre-distortion delay is programmed through the programmable tap weights 109 and depends on the transmission medium that needs to be equalized. Decoder 108 can be embodied and implemented in essentially any suitable manner. For instance, decoder 108 can employ simple Boolean logic to carry out its function as described above. At the same time, the amount of delay to be applied by delay line 110, once the data transition history is known, can depend on the channel at hand. As such, the delay could be pre-set or continuously optimized (if the transmitter can receive information about the channel from the receiving end of the link). [0019] For a typical transmission medium such as coaxial cable where the losses are dominated by frequency dependent attenuation, the high frequency components of a random data sequence arrive first at the end of the transmission medium, while the slowest ones arrives later, as illustrated in the left-hand portion of FIG. 2. Thus, in the illustrative and non-restrictive example shown, the higher-frequency component 250 arrives prior to component 252; the combined graph of these is indicated at 254. The aftereffect, if employed in accordance with the arrangement of FIG. 1, is shown in the right-hand portion of FIG. 2 upon exit from channel 256. Generally, the longest pre-distortion delay is added to the transmitted bit when the transition decoder 108 detects a transition on the previous bit, while the applied delay will be comparably shorter to the extent that the previous transition detected by the transition decoder 108 occurs with "earlier" bits. As shown, with "input" components 250 and 252 now transformed into "output" components 258 and 260, respectively, the former (258) has a comparatively greater delay applied, the result of which can be appreciated in the combined graph at 262 as well as the combined diagram at 264. The marked "DDJ" distance corresponds to this difference in delay. The "eye opening" is the region where data transitions are not present (when considering only DDJ and not jitter due to random noise); as such, data will be detected with no errors if sampled in this region. Continue reading about Data-dependent jitter pre-emphasis for high-speed serial link transmitters... Full patent description for Data-dependent jitter pre-emphasis for high-speed serial link transmitters Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Data-dependent jitter pre-emphasis for high-speed serial link transmitters patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Data-dependent jitter pre-emphasis for high-speed serial link transmitters or other areas of interest. ### Previous Patent Application: Traffic shaping between the dmt processor and data link layer processor of a line-card Next Patent Application: Picture layer rate control for video encoding Industry Class: Pulse or digital communications ### FreshPatents.com Support Thank you for viewing the Data-dependent jitter pre-emphasis for high-speed serial link transmitters patent info. IP-related news and info Results in 0.28824 seconds Other interesting Feshpatents.com categories: Computers: Graphics , I/O , Processors , Dyn. Storage , Static Storage , Printers 174 |
 * Protect your Inventions * US Patent Office filing 
PATENT INFO |
|
