| Data bus mechanism for dynamic source synchronized sampling adjust -> Monitor Keywords |
|
|
  Data bus mechanism for dynamic source synchronized sampling adjustRelated Patent Categories: Electrical Computers And Digital Data Processing Systems: Input/output, Intrasystem Connection (e.g., Bus And Bus Transaction Processing), Bus Access Regulation, Centralized Bus Arbitration, Time-slotted Bus AccessingThe Patent Description & Claims data below is from USPTO Patent Application 20070033313. Brief Patent Description - Full Patent Description - Patent Application Claims
BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to processor system buses, and more particularly to a technique for dynamically adjusting the time at which data on system bus is sampled and provided to a microprocessor core, where the time is based not upon guaranteed data valid time, but upon detection of source synchronous data strobe edges. [0003] 2. Description of the Related Art [0004] A present day sampled data bus, such as may be employed in a microprocessor or integrated circuit (IC) device that communicates over a system bus with other devices to exchange data, receives data from the system bus via data signals. The data signals are indicated as being on the system bus via a data ready signal DRDY that is asserted by the device that is sending the data. The data and DRDY signals are typically asserted and de-asserted in synchronization with a bus clock signal BCLK. According to present day bus protocol, when the sending device drives data onto the data bus, it asserts DRDY, and the states of the data bus signal are guaranteed as being valid on the bus for sampling one cycle of the BCLK later. Accordingly, a present day microprocessor or integrated circuit that is required to receive the data must wait for one cycle of the bus clock BCLK before it samples the data. [0005] Newer protocols for communication of data over a system bus have provided for source synchronous data strobes. The current state of the art provides for a 64-bit data bus DATA that supports transfer during the data phase of a 64-byte cache line over two cycles of a dual bus clock signal BCLK. The transfer of eight bytes over the 64-bit data bus is known as a beat and 4 beats are transferred during each cycle of the bus clock BCLK. In an x86-compatible configuration, the data bus signal group is divided into four subgroups and a pair of data strobes are provided for each data subgroup. Applicable edges (e.g., the falling edges) of each data strobe are used to indicate validity of corresponding words asserted on corresponding subgroups of data. [0006] The present inventor has observed that if conventional techniques for sampling the data signals over a system bus as described herein are employed, disadvantages ensue. First, since four quadwords are transmitted during the BCLK cycle following transmission of another four quadwords, to wait for 1 BCLK cycle before sampling the data would result in unpredictable sampling results. Second, since data strobes are provided to indicate validity of their corresponding doublewords on the data bus, to wait 1 cycle of BCLK before sampling is disadvantageous from a performance standpoint. [0007] It is desired to solve the problem of delay when providing received data elements from a system bus to a processor core due to protocol requirements for data valid times. SUMMARY OF THE INVENTION [0008] A dynamic source synchronized sampling adjust system according to an embodiment of the present invention samples data packets distributed among sequential data beats on a data bus during each of at least one cycle of a bus clock in response to at least one data strobe that is provided for indicating the validity of each data packet. In one embodiment, the dynamic source synchronized sampling adjust system includes first multiplexers, registers, at least one second multiplexer and timing logic. Each first multiplexer has a first input for coupling to the data bus, a second input receiving a corresponding latched data packet, a select input receiving a corresponding one of multiple select signals, and an output. Each register has an input coupled to an output of a corresponding first multiplexer, an output providing a corresponding latched data packet, and a clock input for receiving the data strobe. The second multiplexer has inputs coupled to respective outputs of the registers, an output providing selected latched data packets, and a select input receiving a read pointer. The timing logic has at least one input for receiving the data strobe and outputs providing the select signals. [0009] The first multiplexers and the registers may collectively form a set of muxed-input registers, where each muxed-input register latches a corresponding data packet provided on the data bus. The timing logic may be configured to provide a corresponding select signal to a corresponding first multiplexer when a corresponding data packet is indicated as valid by the data strobe. [0010] In one particular configuration, the data bus is subdivided into subgroups and the data packets are further distributed among the data bus subgroups. Also the data strobe includes at least one data strobe for each data bus subgroup. In this configuration, the timing logic may include multiple sequential timing circuits, each having an input receiving a corresponding data strobe and multiple outputs providing a corresponding subset of the select signals. Each select signal of each subset is provided to a corresponding first multiplexer for selecting a corresponding data packet. The data strobe signal may include a positive data strobe and a negative data strobe. The timing logic includes a sequential timing circuit for each for generating select signals for corresponding data packets. In a more specific configuration, the timing circuit may be implemented as several sequentially-coupled flip-flops which advance through a sequential series of logic states in response to each operative edge of the one or more data strobes. [0011] The dynamic source synchronized sampling adjust system may include a core register having an input coupled to the output of the second multiplexer, an output providing synchronized latched data packets, and a clock input receiving a core clock signal. The read pointer may be synchronized with the core clock signal. [0012] An integrated device for sampling data packets asserted sequentially on a system bus during each of one or more cycles of a bus clock signal in which the system bus includes at least one data strobe signal indicating validity of each data packet according to an embodiment of the present invention includes a clock input for receiving the bus clock signal, a data bus interface for receiving the data packets and for detecting the data strobe signal, and dynamic source synchronized sampling adjust logic. The dynamic source synchronized sampling adjust logic includes sampling logic and select logic. The sampling logic selects and latches each data packet in response to the data strobe signal and provides corresponding latched data packets. The select logic selects from among the latched data packets based on a read pointer. [0013] The sampling logic may include multiplexers, registers and timing logic. Each multiplexer has a first input coupled to the data bus interface, a second input receiving a corresponding latched data packet, and a select input receiving a corresponding select signal. Each register had an input coupled to an output of a corresponding multiplexer, an output providing a corresponding latched data packet, and a clock input for receiving the data strobe. The timing logic has an input for receiving the data strobe and outputs for providing the select signals. [0014] The timing logic of the integrated device may be implemented as sequentially-coupled flip-flops for detecting edges of the data strobe signal. The data strobe signal may include a first data strobe signal indicating validity of a first and every other subsequent data packet asserted sequentially on the system bus and a second data strobe signal indicating validity of a second and every other subsequent data packet asserted sequentially on the system bus. In this case, the timing logic includes first clock logic responsive to the first data strobe signal and second clock logic responsive to the second data strobe signal. [0015] The select logic of the integrated device may be implemented as a multiplexer having inputs coupled to receive the latched data packets, an output providing selected latched data packets, and a select input receiving the read pointer. The integrated device may further include a core register having an input coupled to the output of the multiplexer, an output providing synchronized data packets, and a clock input receiving a core clock signal. In this case, the read pointer may be synchronized with the core clock signal, such as for providing synchronous data to the core of a microprocessor or the like. [0016] A method of sampling data packets asserted sequentially on a data bus for each of at least one cycle of a bus clock according to an embodiment of the present invention includes detecting operative edges of at least one data strobe signal, selecting a corresponding data packet for each operative edge that is detected, and latching each selected data packet to provide latched data packets. [0017] The method may include clocking sequential logic through multiple logic states. The method may include asserting a corresponding select signal for each logic state and providing each select signal to a select input of a corresponding multiplexer coupled to the data bus. The method may include clocking a corresponding register with the data strobe signal. The method may include detecting operative edges of a positive data strobe signal and a negative data strobe signal, and clocking first sequential logic with the positive strobe signal and clocking second sequential logic with the negative strobe signal. The method may include selecting at least one latched data packet and synchronously latching the latched data packet with a core clock signal. [0018] The data packets may be distributed among multiple subgroups of the data bus and among multiple sequential data beats for the at least one cycle of the bus clock. In this case, the at least one data strobe signal may include a separate data strobe signal for each data bus subgroup, and the method includes detecting operative edges of each data strobe signal. BRIEF DESCRIPTION OF THE DRAWINGS [0019] The benefits, features, and advantages of the present invention will become better understood with regard to the following description, and accompanying drawings where: [0020] FIG. 1 is a simplified block diagram of a microprocessor interface system including a data bus mechanism for dynamic source synchronized sampling adjust implemented according to an exemplary embodiment of the present invention; [0021] FIG. 2 is a timing diagram showing the interaction of the signals within the data signal group described with reference to the microprocessor interface system of FIG. 1 for performing the data phase of a quad-pumped data transaction; Continue reading... Full patent description for Data bus mechanism for dynamic source synchronized sampling adjust Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Data bus mechanism for dynamic source synchronized sampling adjust patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Data bus mechanism for dynamic source synchronized sampling adjust or other areas of interest. ### Previous Patent Application: Communication method and device for a motor vehicle Next Patent Application: Enhanced cpu rasum feature in iss servers Industry Class: Electrical computers and digital data processing systems: input/output ### FreshPatents.com Support Thank you for viewing the Data bus mechanism for dynamic source synchronized sampling adjust patent info. IP-related news and info Results in 1.53528 seconds Other interesting Feshpatents.com categories: Novartis , Pfizer , Philips , Polaroid , Procter & Gamble , |
||
