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Cutting cam peak power by clock regioningCutting cam peak power by clock regioning description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20060203529, Cutting cam peak power by clock regioning. Brief Patent Description - Full Patent Description - Patent Application Claims
FIELD OF INVENTION [0001] The present invention relates generally to semiconductor memory devices and, more particularly to peak power reduction in content addressable memory (CAM) devices. BACKGROUND OF THE INVENTION [0002] An essential semiconductor device is semiconductor memory, such as a random access memory (RAM) device. A RAM allows a memory circuit to execute both read and write operations on its memory cells. Typical examples of RAM devices include dynamic random access memory (DRAM) and static random access memory (SRAM). [0003] Another form of memory is the content addressable memory (CAM) device. A CAM is a memory device that accelerates any application requiring fast searches of a database, list, or pattern, such as in database machines, image or voice recognition, or computer and communication networks. CAMs provide benefits over other memory search algorithms by simultaneously comparing the desired information (i.e., data in the comparand register) against the entire list of pre-stored entries. As a result of their unique searching algorithm, CAM devices are frequently employed in network equipment, particularly routers and switches, computer systems and other devices that require rapid content searching. [0004] In order to perform a memory search in the above-identified manner, CAMs are organized differently than other memory devices (e.g., DRAM). For example, data is stored in a RAM in a particular location, called an address. During a memory access, the user supplies an address and writes into or reads the data at the specified address. [0005] In a CAM, however, data is stored in locations in a somewhat random fashion. The locations can be selected by an address bus, or the data can be written into the first empty memory location. Every memory location includes one or more status bits which maintain state information regarding the memory location. For example, each memory location may include a valid bit whose state indicate whether the memory location stores valid information, or whether the memory location does not contain valid information (and is therefore available for writing). [0006] Once information is stored in a memory location, it is found by comparing every bit in a memory location with corresponding bits in a comparand register. When the content stored in the CAM memory location does not match the data in the comparand register, a local match detection circuit returns a no match indication. When the content stored in the CAM memory location matches the data in the comparand register, the local match detection circuit returns a match indication. If one or more local match detect circuits return a match indication, the CAM device returns a "match" indication. Otherwise, the CAM device returns a "no-match" indication. In addition, the CAM may return the identification of the address location in which desired data is stored or identification of one of such addresses if more than one address contained matching data. Thus, with a CAM, the user supplies the data and gets back an address if there is a match found in memory. [0007] FIG. 1 is a circuit diagram showing a conventional DRAM-based CAM cell 100, which includes two one-transistor (1T) DRAM cells 110a and 110b, and a four-transistor comparator circuit 120 made up of four transistors Q2, Q3, Q4, and Q5. Although FIG. 1 illustrates a DRAM-based CAM cell 100, it should be recognized that CAM devices can also be made using SRAM-based CAM cells. The DRAM cells 110a and 110b are used to store values. Generally, the content of the first cell 110a is the logical complement of the content of the second cell 110b. However, the cells 110a, 110b may also store the same values, i.e., "1"/"1", or "0"/"0", so that the CAM cell 100 is respectively set to "always match" or "always mismatch" states. [0008] The first DRAM cell 110a includes transistor Q1 and capacitor CA, which combine to form a storage node A that receives a data value from a first bit line BL1 at node U during write operations, and applies the stored data value to the gate terminal of transistor Q2 of comparator circuit 120. Transistor Q2 is connected in series with transistor Q3 between a match line M and a ground potential. Transistor Q3 is controlled by a data signal transmitted on data line D1#. The second DRAM cell 110b includes transistor Q3 and capacitor CB, which combine to form a storage node B that receives a data value from a second bit line BL2 at node V, and applies the stored data value to the gate terminal of transistor Q4 of comparator circuit 120. Transistor Q4 is connected in series with transistor Q5 between the match line M and the ground potential. It should be noted that in some embodiments transistors Q2 and Q4 are coupled to a discharge line instead of being directly coupled to ground. Transistor Q5 is controlled by a data signal transmitted on data line D1, between the match line and the ground potential. [0009] FIG. 2 is a block diagram of a conventional CAM device 200. The device 200 includes a CAM array 210 of cells 100 (FIG. 1). While the array 210 is illustrated as a single array, depending upon the number of cells 100, the array 210 may be replaced with a plurality of arrays. As illustrated, each row of cells 100 is coupled to a same match line M, which is also coupled, via a respective sense amplifier 230, to a priority encoder 240. The array 210 includes other well known components, such as bit lines, word lines, additional sense amplifiers, precharge circuits, refresh circuits, etc., which are not illustrated to simplify FIG. 2. The array 210 is also coupled to a comparand regiser 220, which is used to supply a search pattern to the array 210. The array 210, comparand register 220, and the priority encoder 240 are each coupled to control logic 250. The control logic 250, which is also coupled to data lines 251, address lines 252, control lines 253, and at least one clock line 254, controls the operation of the CAM device 200. [0010] Now referring back to FIG. 1, when a match operation portion of the search is performed, data stored at nodes A and B of a cell 100 are respectively applied to the gate terminals of transistors Q2 and Q4 of comparator circuit 120. Comparator circuit 120 is utilized to perform match (comparison) operations after the match line M has been precharged by a precharge circuit (not illustrated). For example, when the match line M is precharged, an applied data value and its complement are transmitted on data lines D1 and D1# to the gate terminals of transistors Q3 and Q5, respectively. A no-match condition is detected when match line M is discharged to ground through the signal path formed by transistors Q2 and Q3, or through the signal path formed by transistors Q4 and Q5. For example, when the stored data value at node A and the applied data value transmitted on data line D1# are both logic "1", then both transistors Q2 and Q3 are turned on to discharge match line M to ground. This occurs because D1# should be the complement of the data at node A. When a match condition occurs, match line M remains in its precharged state (i.e., no signal path is formed by transistors Q2 and Q3, or transistors Q4 and Q5). [0011] The above described match operation illustrates what happens in a single CAM cell 100. In the device 200, however, the match operation is performed simultaneously on all CAM cells 100. This permits search operations to be performed much faster on a CAM device than a conventional memory device, such as a DRAM. However, CAM devices 200 consume significantly more power and produce significantly more switching noise than a conventional memory device, especially during a first portion of the search operation because the CAM cells 100 are accessed and searched simultaneously. This results in the CAM device 200 having a peak power consumption which may be significantly higher than the average power consumption during a portion of each match operation. The high peak power consumption requires the CAM device 200 to be used with a robust power supply, and also increases heat production. Both of these effects are undesirable and should be minimized. Accordingly, there is a need for a CAM device architecture that has a lesser degree of peak power consumption. SUMMARY OF THE INVENTION [0012] The invention provides a CAM device architecture where the CAM cells are divided into at least two arrays. Each array is operated in a different clock domain so that each array is prevented from drawing maximum power at a same time. By dividing the CAM array into a plurality of arrays and staggering the search operation so that every array does not simultaneously draw maximum power, the peak power consumption of the CAM device is reduced. BRIEF DESCRIPTION OF THE DRAWINGS [0013] The foregoing and other advantages and features of the invention will become more apparent from the detailed description of exemplary embodiments of the invention given below with reference to the accompanying drawings, in which: [0014] FIG. 1 is a circuit diagram of a conventional CAM cell; [0015] FIG. 2 is a block diagram of a conventional CAM device; [0016] FIG. 3A is a block diagram illustrating a first exemplary embodiment of the invention; [0017] FIG. 3B is a timing diagram illustrating the operation sequence of the first embodiment of the invention; [0018] FIG. 4A is a block diagram illustrating a second exemplary embodiment of the invention; [0019] FIG. 4B is a timing diagram illustrating the operation sequence of the second embodiment of the invention; [0020] FIG. 5. is a block diagram of a processor based system having a CAM device constructed in accordance with the principles of the present invention; and Continue reading about Cutting cam peak power by clock regioning... Full patent description for Cutting cam peak power by clock regioning Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Cutting cam peak power by clock regioning patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Cutting cam peak power by clock regioning or other areas of interest. ### Previous Patent Application: Compact ternary and binary cam bitcell architecture with no enclosed diffusion areas Next Patent Application: Early read after write operation memory device, system and method Industry Class: Static information storage and retrieval ### FreshPatents.com Support Thank you for viewing the Cutting cam peak power by clock regioning patent info. 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