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  Creation and management of routing table for pci bus address based routing with integrated didRelated Patent Categories: Multiplex Communications, Pathfinding Or RoutingThe Patent Description & Claims data below is from USPTO Patent Application 20070165596. Brief Patent Description - Full Patent Description - Patent Application Claims
BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The invention disclosed and claimed herein generally pertains to a method and related apparatus for routing PCIe transaction packets between multiple hosts and adapters, through a PCIe switched-fabric. More particularly, the invention pertains to a method for creating and managing the structures needed for routing PCI transaction packets between multiple hosts and adapters when using a Destination Identification (DID) that is integrated into the PBA. [0003] 2. Description of the Related Art [0004] As is well known by those of skill in the art, PCI Express (PCIe) is widely used in computer systems to interconnect host units to adapters or other components, by means of a PCI switched-fabric bus or the like. However, PCIe currently does not permit the sharing of input/output (I/O) adapters in topologies where there are multiple hosts with multiple shared PCIe links. As a result, even though such sharing capability could be very valuable when using blade clusters or other clustered servers, adapters for PCIe and secondary networks (e.g., FC, IB, Enet) are at present generally placed only into individual blades and server systems. Thus, such adapters cannot be shared between clustered blades, or even between multiple roots within a clustered system. [0005] In an environment containing multiple blades or blade clusters, it can be very costly to dedicate a PCI adapter for use with only a single blade. For example, a 10 Gigabit Ethernet (10 GigE) adapter currently costs on the order of $6,000. The inability to share these expensive adapters between blades has, in fact, contributed to the slow adoption rate of certain new network technologies such as 10 GigE. Moreover, there is a constraint imposed by the limited space available in blades to accommodate I/O adapters. This problem of limited space could be overcome if a PC network was able to support attachment of multiple hosts to a single PCI adapter, so that virtual PCIe I/O adapters could be shared between the multiple hosts. [0006] In order to allow virtualization of PCIe adapters in the above environment, a mechanism is required for creating and managing the structures needed for routing PCI transaction packets between multiple hosts and adapters. The mechanism must be designed so that it protects memory and data in the system image of one host from being accessed by unauthorized applications in system images of other hosts. Access by other adapters in the same PCI tree must also be prevented. Moreover, implementation of the mechanism should minimize changes that must be made to currently used PCI hardware. SUMMARY OF THE INVENTION [0007] The invention is generally directed to the provision and management of tables for routing packets through an environment that includes multiple hosts and shared PCIe switches and adapters. The invention features modification of a conventional PCI Bus Address (PBA) by including a Destination Identification (DID) field in the PBA. Thus, the DID field is embedded in a transaction packet dispatched through the PCIe switches, and is integrated into the PCI address. A particular DID is associated with a particular host or system image, and thus identifies the physical or virtual end point of its packet. One useful embodiment of the invention is directed to a method for creating and managing the structures needed for routing PCIe transaction packets through PCIe switches in a distributed computer system comprising multiple root nodes, wherein each root node includes one or more hosts. The system further includes one or more PCI adapters. A physical tree that is indicative of a physical configuration of the distributed computing system is determined, and a virtual tree is created from the physical tree. The virtual tree is then modified to change an association between at least one source device and at least one target device in the virtual tree. A validation mechanism validates the changed association between the at least one source device and the at least one target device to enable routing of data from the at least one source device to the at least one target device. BRIEF DESCRIPTION OF THE DRAWINGS [0008] FIG. 1 is a block diagram showing a generic distributed computer system for use with an embodiment of the invention. [0009] FIG. 2 is a block diagram showing an exemplary logical partition platform in the system of FIG. 1. [0010] FIG. 3 is a block diagram showing a distributed computer system in further detail, wherein the system of FIG. 3 is adapted to implement an embodiment of the invention. [0011] FIG. 4 is a schematic diagram depicting several PCI Bus Addresses, each with an integrated DID component and associated with either a Root Complex or a Virtual End Point for use in an embodiment of the invention. [0012] FIG. 5 is a schematic diagram showing a PCI-E transaction packet, together with a simplified Integrated Destination ID Routing Table and a simplified Integrated Destination ID Validation Table, according to an embodiment of the invention. [0013] FIG. 6 illustrates a PCI configuration header according to an exemplary embodiment of the present invention; [0014] FIG. 7 presents diagrams that schematically illustrate a system for managing the routing of data in a distributed computing system according to an exemplary embodiment of the present invention; [0015] FIG. 8 is a flowchart that illustrates a method for managing the routing of data in a distributed computing system according to an exemplary embodiment of the present invention; and [0016] FIG. 9 is a flowchart that illustrates a method for assigning source and destination identifiers in connection with managing the routing of data in a distributed computing system according to an exemplary embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT [0017] FIG. 1 shows a distributed computer system 100 comprising a preferred embodiment of the present invention. The distributed computer system 100 in FIG. 1 takes the form of multiple root complexes (RCs) 110, 120, 130, 140 and 142, respectively connected to an I/O switched-fabric bus 144 through I/O links 150, 152, 154, 156 and 158, and to the memory controllers 108, 118, 128 and 138 of the root nodes (RNs) 160-166. The I/O fabric is attached to I/O adapters (IOAs) 168-178 through links 180-194. The IOAs may be single function, such as IOAs 168-170 and 176, or multiple function, such as IOAs 172-174 and 178. Moreover, respective IOAs may be connected to the I/O fabric 144 via single links, such as links 180-186, or with multiple links for redundancy, such as links 188-194. [0018] The RCs 110, 120, and 130 are integral components of RN 160, 162 and 164, respectively. There may be more than one RC in an RN, such as RCs 140 and 142 which are both integral components of RN 166. In addition to the RCs, each RN consists of one or more Central Processing Units (CPUs) 102-104, 112-114, 122-124 and 132-134, memories 106, 116, 126 and 136, and memory controllers 108, 118, 128 and 138. The memory controllers respectively interconnect the CPUS, memory, and I/O RCs of their corresponding RNs, and perform such functions as handling the coherency traffic for respective memories. [0019] RN's may be connected together at their memory controllers, such as by a link 146 extending between memory controllers 108 and 118 of RNs 160 and 162. This forms one coherency domain which may act as a single Symmetric Multi-Processing (SMP) system. Alternatively, nodes may be independent from one another with separate coherency domains as in RNs 164 and 166. [0020] FIG. 1 shows a PCI Configuration Manager (PCM) 148 incorporated into one of the RNs, such as RN 160, as an integral component thereof. The PCM configures the shared resources of the I/O fabric and assigns resources to the RNs. Continue reading... Full patent description for Creation and management of routing table for pci bus address based routing with integrated did Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Creation and management of routing table for pci bus address based routing with integrated did patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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