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05/24/07 | 70 views | #20070118725 | Prev - Next | USPTO Class 712 | About this Page  712 rss/xml feed  monitor keywords

Cpu life-extension apparatus and method

USPTO Application #: 20070118725
Title: Cpu life-extension apparatus and method
Abstract: A CPU life-extension apparatus and method makes a processor appear to be an upgraded CPU to substantially all software applications accessed thereby, thereby reducing the need and expense of upgrading a selected processor. A CPU life-extension module translates new instructions, intended for a CPU upgrade, into instructions recognized by the processor. In addition, the CPU life-extension module is programmed to monitor reads from and writes to a processor's flags register to modify the flags to emulate those of an upgraded CPU. The CPU life-extension module is configured to respond to interrupts generated by the processor in order to perform its various tasks. (end of abstract)
Agent: Pate Pierce & Baird - Salt Lake City, UT, US
Inventor: Phillip M. Adams
USPTO Applicaton #: 20070118725 - Class: 712209000 (USPTO)
Related Patent Categories: Electrical Computers And Digital Processing Systems: Processing Architectures And Instruction Processing (e.g., Processors), Instruction Decoding (e.g., By Microinstruction, Start Address Generator, Hardwired), Decoding Instruction To Accommodate Plural Instruction Interpretations (e.g., Different Dialects, Languages, Emulation, Etc.)
The Patent Description & Claims data below is from USPTO Patent Application 20070118725.
Brief Patent Description - Full Patent Description - Patent Application Claims  monitor keywords

1. RELATED APPLICATIONS

[0001] This application is a continuation of U.S. patent application Ser. No. 10/155,284 filed May 23, 2002 and entitled CPU LIFE-EXTENSION APPARATUS AND METHOD.

BACKGROUND

[0002] 2. The Field of the Invention

[0003] This invention relates to computer systems and, more particularly, to novel systems and methods for extending the instruction set of existing CPUs via software "welding" techniques.

[0004] 3. The Background Art

[0005] A CPU, also known as a processor, is the processing center of a computer system. A CPU may be designed with a collection of machine language instructions, or instruction set, that the processor understands and follows. Program code, developed to perform a desired task, must ultimately perform its various functions and routines using the instruction set of the processor on which it is processed. As CPU manufacturers, such as Intel, have released newer and faster processor architectures, one hallmark of their evolution and design has been backward compatibility, meaning that newer chips will execute the instruction set of previous processors. However, program code written for newer architectures may not run on the older processors, since new instructions may be utilized. In some cases, the instruction set of a new CPU architecture may only include a few new instructions as compared to those of its predecessor.

[0006] For example, the Intel 80486 (the 486) processor architecture added 6 new instructions to extend its Intel 80386 (the 386) instruction set core. Likewise, the Intel Pentium added 8 new instructions to its 486 instruction set core. In some cases, software may utilize the new instructions, and therefore, not run on older processors. These new instructions, if encountered by an older processor, may incur errors in the operation thereof, and may cause a system shutdown or the like.

[0007] As new instructions are added, some software may check the characteristics, such as clock speed, architecture, and the like, of the processor on which it is running. Certain instructions, when executed, simply identify selected characteristics of the processor. These characteristics may be used like flags by the software to decide whether to proceed with execution or to modify execution in some way. For example, the CPUID instruction, introduced to the core instruction set in upgraded processors, may return the values of certain characteristics of a given processor. Some processors may not support this instruction and will, therefore, incur errors when encountering it.

[0008] Installation programs, used to install many software applications, may check the characteristics of a processor and require that a computer meet a pre-selected set of requirements. For example, a purchased software package may state on its packaging a minimum CPU architecture, clock speed, RAM requirements, secondary storage (disk capacity) requirements, or a combination thereof to operate the software. If these minimum system requirements are not met, the installation program may abort the installation process and prevent a user from installing the desired software.

[0009] Some software manufacturers may justify this action in order to ensure that a software package performs at what the manufacturer considers a satisfactory level. Unfortunately, some requirements may be artificially imposed. That is, a program may actually run at a satisfactory performance level, as deemed by a user of a computer system, but the user may be prevented from installing and running the software because the manufacturer has artificially locked out selected computer systems. In a sense, the manufacturer of the software has forced obsolescence of the computer system, as in the case of Microsoft and the Windows operating system. This may require a user to unnecessarily upgrade or purchase a new computer system, satisfying the requirements, incurring unneeded frustration, effort, collateral programming, and expense to the user.

[0010] In accordance with the issues and problems described hereinbefore, what is needed is a software solution whereby an older processor may emulate a newer processor's extended features without incurring a significant performance penalty, thereby eliminating the need to unnecessarily upgrade to a newer processor or computer system to host newer operating systems and software.

[0011] What is further needed is a software solution to make an older processor indistinguishable from a newer processor or a CPU upgrade to substantially all software accessed thereby, providing the same features and functionality.

[0012] What is further needed is a method to effectively seamlessly integrate, "weld", such a software solution into the operation of an older processor, in order to mediate and monitor all access and use of the processor to replicate an upgraded or later model processor's behavior.

BRIEF SUMMARY AND OBJECTS OF THE INVENTION

[0013] In view of the foregoing, it is desirable to provide a CPU life-extension module that may render a previous CPU indistinguishable from an upgraded CPU to virtually or substantially all operating systems and applications running thereon. Not only may the CPU "appear" to be an upgraded CPU to all software, but the CPU life-extension module may provide the same substantive features and functionality of an upgraded CPU. Thus, the useful life of a CPU may be extended and needless effort and expense may be avoided by the owners and users thereof. In addition, artificial locks and barriers, designed to prevent users from installing and using selected software, may be bypassed.

[0014] While some software may utilize newer instructions intended for an upgraded CPU, in many cases, the use of these new instructions may be relatively rare. In some cases, new instructions may only be used to identify and reject "old" processors during installation, and never occur again. In other cases, software may be artificially prevented from running on a particular processor simply due to the lack of a "new" instruction despite the fact that it is not using any of the "new" instructions. In many cases, software, utilizing new instructions may run quite satisfactorily on an older processor if the relatively few newer instructions could be translated into the older processor's native instruction set. Since the new instructions occur relatively infrequently, this translation process may result in very little performance degradation.

[0015] Consistent with the foregoing needs, and in accordance with the invention as embodied and broadly described herein, a method and apparatus are disclosed in one embodiment in accordance with the invention as including a processor configured to process data structures comprising executable and operational data. The processor may have a native instruction set that software may use to perform various tasks. A memory device may be operably connected to the processor to store the data structures.

[0016] In accordance with the invention, the data structures may include a CPU life-extension module configured to run on the processor and implement new instructions contained in an upgraded CPU's instruction set. The CPU life-extension module may augment the native instruction set of the processor to include additional instructions not previously recognized by the processor.

[0017] The CPU life-extension module may be further configured to intervene, when needed, between the processor and data structures processed by the processor, such as applications and the operating system, in order to "appear" to software as an upgraded CPU and to provide the same features and functionality of the upgraded CPU. In certain embodiments, the user may actually be able to choose the extensions to be applied to the CPU. In order to intervene between the processor and the operating system, in certain embodiments, the CPU life-extension module may be installed as a driver. This may allow the CPU life-extension module access to the processor at the highest privilege level.

[0018] The processor may be programmed to generate interrupts in response to system faults. The CPU life-extension module may be configured to perform its tasks in response to these interrupts. For example, the CPU life-extension module may be programmed to translate additional instructions, not recognized by the processor, into the processor's native instruction set for processing. This may be accomplished either statically when an application is being loaded or dynamically during execution by responding to an interrupt, generated by the processor, whenever an invalid operation code is encountered. An invalid operation code handler may be invoked that may translate the unrecognized operation code into operation codes recognized by the processor. If the operation code is not recognized by the CPU life-extension module, then the normal invalid operation code procedures may be invoked.

[0019] An apparatus and method in accordance with the invention may be programmed to modify system flags to emulate those of an upgraded CPU. For example, a processor may include a flags register containing flags to reflect system status. These flags may indicate whether or not a processor includes various features and functions. The CPU life-extension module may be programmed to detect READ instructions from and WRITE instructions to the flags register and modify the reads and writes to reflect an "extended" flag status corresponding to a CPU in an upgraded state. In certain embodiments, this may be accomplished by maintaining a virtual flags register within the CPU life-extension module.

[0020] An apparatus and method in accordance with the invention may configure the processor to generate a stack-fault interrupt whenever the processor pushes data onto the processor's stack. This may be accomplished, in part, by setting the stack size value equal to the address of the current top of the stack. Thus, a stack-fault handler may then be invoked whenever a value is pushed onto the stack. The stack-fault handler may then determine if the operation is pushing values of a flags register onto the stack, and if so, increment the stack size to allow the flags register to be pushed onto the stack, push the flags register onto the stack, and then modify the flag values to emulate those of an upgraded CPU. Thus, in certain embodiments, the modification of the flags register may occur in the copy thereof contained on the stack.

[0021] In a similar manner, the stack-fault handler module may be configured to detect future pop operations (e.g. operations pulling values off of the stack), corresponding to push operations (e.g. operations placing values onto the stack), and set breakpoint interrupts to occur in response to the pop operations. A breakpoint handler may then be invoked to decrease the stack size whenever a pop operation occurs. Thus, future push operations will continue to incur a stack-fault interrupt whenever executed. In other embodiments, the stack size may be maintained using approaches such as stack "shadowing", which may maintain a zero-size stack by always invoking a fault handler.

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