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  Controlling execution of a block of program instructions within a computer processing systemRelated Patent Categories: Electrical Computers And Digital Processing Systems: Processing Architectures And Instruction Processing (e.g., Processors), Processing Control, Branching (e.g., Delayed Branch, Loop Control, Branch Predict, Interrupt), To Macro-instruction RoutineControlling execution of a block of program instructions within a computer processing system description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20050257037, Controlling execution of a block of program instructions within a computer processing system. Brief Patent Description - Full Patent Description - Patent Application Claims
BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to the field of data processing systems. More particularly, the present invention relates to the control of execution of a block of program instructions within a data processing system. [0003] 2. Description of the Prior Art [0004] It is known that computer programs often contain sequences of program instructions that are frequently repeated within the computer program. In order to produce a computer program with a smaller code size, it is known to arrange such blocks of computer program instructions into functions or subroutines which can be called from various positions within the computer program. [0005] It is normal for such subroutines to terminate with a return instruction which commands the data processing system to return to the instruction immediately following the point in the computer program from where the call to the subroutine was made. When the subroutine or block of instructions is short in length, then the overhead of providing a return instruction at the end of the subroutine can form a significant proportion of the size of the subroutine itself. As an example, if the subroutine block of program instructions being called is only three instructions in length, then the necessary return instruction at the end of the block increases this length to four instructions and results in a significant increase in code size when this is repeated across a large number of such subroutines which may be included within a computer program as a whole. [0006] It is also known within VAX architecture computers to provide an execute instruction which commands the system to execute an instruction found at a memory location specified by the execute instruction. This type of operation can be considered as a one-for-one replacement of the execute instruction within the program code by different instructions pointed to by those execute instructions. This type of functionality is particularly useful for debugging and diagnostic purposes but does not yield significant code density improvements. [0007] It is also known to provide data processing systems including a dictionary function whereby an instruction in the program is a dictionary instruction which triggers a reference to be made to a stored dictionary table where there is a pointer to a memory location storing a sequence of program instructions to be executed in response to that dictionary function. The dictionary table may also include an indication of the length of that block of instructions. The dictionary table approach has the disadvantage that an additional memory construct, namely the dictionary table, needs to be provided within the data processing system as well as additional registers for keeping track of full length memory addresses for the dictionary instruction and the position within the block of program instructions called. In the context of blocks of program instructions which are very short in length, the storage requirements of the dictionary table entries relating to those small blocks of program instructions form a significant proportion of the storage requirements for those blocks of instructions in a manner which is disadvantageous. [0008] A further disadvantage of the dictionary table approach is that it is a more radical change to an existing data processing system architecture if it is to be added to such an existing data processing system architecture. [0009] It is desired to provide a technique whereby frequently repeated sequences of program instructions within a computer program can be executed by a data processing apparatus in an efficient manner whilst minimising the degree of any architectural changes which may be required. SUMMARY OF THE INVENTION [0010] Viewed from one aspect the present invention provides a data processing apparatus comprising: an instruction fetching circuit operable to fetch a sequence of program instructions from a sequence of memory locations; an instruction decoder responsive to program instructions within the sequence of program instructions fetched by the instruction fetching circuit to control data processing operations specified by the program instructions; and an execution circuit operable under control of the instruction decoder to execute the data processing operations, wherein the instruction decoder is responsive to an execute block instruction within the sequence of program instructions to trigger fetching of a block of two or more program instructions by the instruction fetching circuit and execution of the block of two or more program instructions by the execution circuit, the block of two or more instructions containing a number of program instructions specified by a block length field within the executed block instruction and being stored at a memory location specified by a location field within the execute block instruction, the apparatus further comprising execute block instruction logic operable in response to the execute block instruction to store an indication of a memory location of an instruction following the execute block instruction and to determine which instruction in the block of two or more program instructions is being processed, the execute block instruction logic being further operable when it is determined that a last instruction in the block of two or more program instructions is being processed to provide to the instruction fetching circuit the indication of the memory location of the instruction following the execute block instruction so that the instruction following the execute block instruction is fetched for execution immediately following the last instruction in the block of two or more program instructions. [0011] The present technique recognises that for a large number of blocks of program instructions that can advantageously be the subject of calls from different points within a program, the return instruction represents a significant overhead. Combined with this is the realisation that such small blocks of program instructions rarely need to include therein branch instructions such that when they are started they will with a high degree of probability always be run to their conclusion, i.e. result in a fixed number of program instructions being fetched and executed. Accordingly, the execute block instruction provided by the present technique specifies within the execute block instruction both the location of the block of program instructions to be executed as well as the length of that block of program instructions. Accordingly, there is no need for the block of program instructions to include a return instruction, since the length of the block is already known as specified within the execute block instruction and the return to the main program can be triggered when the final instruction within the block of program instructions has been executed. This execute block instruction extends the advantages of program instruction calls to small blocks of program instructions. The technique is also particularly well suited to use by program compilers which can identify frequently occurring small blocks of instructions within a program image and replace these by execute block instructions. The occurrence of a block in the normal code can be used as the target of branch instructions without the need to separately store the block of instructions elsewhere. [0012] Also, the present invention further recognises that even when the last instruction in the block of instructions is not itself a branch instruction, this instruction can be viewed as a branch instruction in addition to the encoded data processing operation. This is because, in typical operation, a return will occur to an instruction following the execute block instruction. Hence, a non-sequential instruction or operation will be required to be executed following execution of that last instruction. However, it will be appreciated that the last instruction itself would not typically provide an indication of the memory location of the instruction following execute block instruction or contain any information which would normally enable such an indication to be provided. Also, because the last instruction is typically not an instruction which would normally be interpreted as being encoded as a branch, the likelihood that executing that instruction will result in a branch would not normally ever be considered as a possibility and, hence, the fetch unit would typically assume that it is required to linearly access instructions following the last instruction. It will be appreciated that once the last instruction is executed, a recognition will be made that a non-sequential instruction is needed to be executed next. However, this instruction would not have been fetched by the fetch unit and so any following instructions will need to be flushed whilst the required instruction is fetched and processed. It will be appreciated that this situation will occur typically relatively frequently since, in order to maximise code compression, the occurrence of execute block instructions may be high. Accordingly, the number of flushes that would need to be performed would also be relatively high, which may have an adverse effect on overall performance. [0013] Accordingly, execute block instruction logic is provided which stores an indication of a memory location of an instruction following the execute block instruction. The execute block instruction logic determines when the last instruction in the block of two or more program instructions is being processed. When it is determined that the last instruction in the block of two or more program instructions is being processed then an indication of the memory location of an instruction following the execute block instruction is provided to the instruction fetching circuit. Providing the indication of the memory location of the instruction following the execute block instruction to the instruction fetching circuit causes the fetch unit to fetch that instruction. It will be appreciated that in some fetch units which take multiple cycles to fetch instructions or where the fetch unit fetches blocks of instructions, one or more instructions linearly following the last instruction may still be fetched by the fetch unit but these instructions will not be executed. In this way, the correct sequence of instructions is fetched by the fetch unit which avoids the need to flush instructions, with all the attendant performance implications which result from such flushing. Hence, it will be appreciated that the provision of the execute block logic enables the execute block instruction to be implemented in an efficient manner whilst minimising the degree of any architectural changes which may be required. [0014] In embodiments, the execute block instruction logic is operable in response to the execute block instruction to store an indication of the memory location specified by the location field within the execute block instruction, the execute block instruction logic being further operable when it is determined that the execute block instruction is being processed to provide to the instruction fetching circuit the indication of the memory location specified by the location field within the execute block instruction so that instructions in the block of two or more program instructions are fetched for execution immediately following the execute block instruction. [0015] Accordingly, execute block instruction logic is provided which stores an indication of a memory location of an instruction pointed to by the location field within the execute block instruction. The execute block instruction logic determines when the execute block instruction is being processed. When it is determined that the execute block instruction is being processed then an indication of the memory location of the instruction referred to by the execute block instruction is provided to the instruction fetching circuit. Providing the indication of the memory location of the instruction referenced to the execute block instruction to the instruction fetching circuit causes the fetch unit to fetch that instruction. As mentioned previously, in fetch units which take multiple cycles to fetch instructions or where the fetch unit fetches blocks of instructions, one or more instructions sequentially following the execute block instruction may still be fetched by the fetch unit but these instructions will not be executed. In this way, the correct sequence of instructions is fetched by the fetch unit which avoids the need to flush instructions, with all the attendant performance implications which result from such flushing. [0016] In embodiments, the execute block instruction logic comprises storage operable to store the indication of the memory location of the instruction following the execute block instruction, which indication being associated as a target memory location with the last instruction in the block of two or more program instructions. [0017] In embodiments, the storage is further operable to store the indication of the memory location specified by the location field within the execute block instruction, which indication being associated as a target memory location with the execute block instruction. [0018] It will be appreciated that the storage could be provided anywhere in the data processing apparatus. In embodiments, the storage is a branch target buffer, associated with the fetch circuit. [0019] In embodiments, the storage contains a number of entries, each entry having a field for storing an indication of the memory location of an instruction and an associated field for storing an indication of a corresponding target memory location. [0020] Hence, the storage is arranged to readily associate instructions with target instruction memory locations. In embodiments, each entry comprises further fields. [0021] In embodiments, the storage comprises a return stack operable to store the indication of the memory location of the instruction following the execute block instruction, which indication being associated as the target memory location with the last instruction in the block of two or more program instructions. [0022] Such a return stack will typically be arranged to store the indications in a first-in, last-out arrangement. The return stack may or may not be shared with normal subroutines and, if not shared, may degenerate to a single entry (single execute block) return buffer. Continue reading about Controlling execution of a block of program instructions within a computer processing system... Full patent description for Controlling execution of a block of program instructions within a computer processing system Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Controlling execution of a block of program instructions within a computer processing system patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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