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  Controlled growth of highly uniform, oxide layers, especially ultrathin layersUSPTO Application #: 20070218668Title: Controlled growth of highly uniform, oxide layers, especially ultrathin layers Abstract: The present invention relates to methods of making oxide layers, preferably ultrathin oxide layers, with a high level of uniformity. One such method includes the steps of forming a substantially saturated or saturated oxide layer directly or indirectly on a semiconductor surface of a semiconductor substrate, and etchingly reducing the thickness of the substantially saturated or saturated oxide layer by an amount such that the etched oxide layer has a thickness less than the substantially saturated or saturated oxide layer. In certain embodiments, methods of the present invention provide etched oxide layers with a uniformity of less than about +/−10%. The present invention also relates to microelectronic devices including made by methods of the present invention and manufacturing systems for carrying out methods of the present invention. (end of abstract) Agent: Kagan Binder, PLLC - Stillwater, MN, US Inventor: Thomas J. Wagener USPTO Applicaton #: 20070218668 - Class: 438591000 (USPTO) Related Patent Categories: Semiconductor Device Manufacturing: Process, Coating With Electrically Or Thermally Conductive Material, Insulated Gate Formation, Gate Insulator Structure Constructed Of Plural Layers Or Nonsilicon Containing Compound The Patent Description & Claims data below is from USPTO Patent Application 20070218668. Brief Patent Description - Full Patent Description - Patent Application Claims
REFERENCE TO PRIOR FILED APPLICATIONS [0001] This patent Application is a continuation of and is entitled to the benefit of the filing date of prior nonprovisional patent Application No. 10/900,912, filed on Jul. 28, 2004, by Thomas J. Wagener, and titled CONTROLLED GROWTH OF HIGHLY UNIFORM, OXIDE LAYERS, ESPECIALLY ULTRATHIN LAYERS, which nonprovisional patent application claims priority of commonly owned provisional Application Ser. No. 60/491,850, filed on Jul. 31, 2003, and titled CONTROLLED GROWTH OF HIGHLY UNIFORM, OXIDE LAYERS, ESPECIALLY ULTRATHIN LAYERS, wherein the entireties of said prior patent Applications are incorporated herein by reference. FIELD OF THE INVENTION [0002] The present invention provides methodologies to precisely form ultrathin oxide layers having excellent uniformity and purity characteristics. The layers may be used in a wide range of applications, but are especially useful as buffer layers for higher k dielectric materials when making gate dielectric structures. BACKGROUND OF THE INVENTION [0003] Most integrated circuits currently produced are manufactured on thin disks of silicon and/or other semiconductor material (wafers) using "complementary metal oxide semiconductor" (CMOS) technology. A general discussion of CMOS technology can be found in "Silicon Processing for the VLSI Era, Volume 2--Process Integration" by Wolf et al., Lattice Press, 298-367, (1990). In a CMOS circuit, an electric potential applied to a transistor's gate electrode capacitively couples to its channel and controls the current that flows between its source and drain electrodes. The gate electrode is electrically insulated from the channel by the gate dielectric. The gate dielectric has historically utilized SiO.sub.2 formed by thermally oxidizing the silicon above the channel. SiO.sub.2 dielectrics have many advantages, including their ability to be removed by etching in either gas, plasma or liquid based processes. [0004] The electrical properties of the transistor depend to a significant degree upon the nature of the gate dielectric. In particular, reducing the thickness of the dielectric increases the capacitive coupling between the gate and channel, allowing higher speed transistor operation at lower operating voltages. But, as the thickness of the dielectric is reduced much below about 20 angstroms, quantum tunneling effects tend to increase, allowing an electric current to flow between the gate and channel. This tunneling current is undesirable as it increases the transistor's power requirements and causes undue heat generation. [0005] Excessive tunneling can be alleviated if the capacitive coupling between the gate and channel is increased by increasing the dielectric constant (k) of a fixed "physical" thickness of gate dielectric, t.sub.phys. In one approach, then, a portion or all of a gate dielectric layer can be replaced with an equivalent "electrical thickness" of an insulating material having a dielectic constant that is higher than that of silicon dioxide. The equivalent "electrical thickness," t.sub.elect, of a high-k gate dielectric is approximately equal to the gate's physical thickness times the ratio of the dielectric constants of SiO.sub.2 and the high-k material, k.sub.SiO2 and k.sub.high-k, respectively. That is: t.sub.elect=t.sub.phys*(k.sub.SiO2/k.sub.high-k) [0006] For example, assume it is desired to form a gate dielectric layer having the electrical capacitance of a silicon dioxide layer that is 10 angstroms thick. Because of quantum tunneling effects, actually using a silicon dioxide layer that is only ten angstroms thick is problematic. However, recognizing that silicon dioxide has a dielectric constant of 3.8, one generally instead can use 20 angstroms of a material whose dielectric constant is 7.6, or 30 angstrom of a material whose dielectric constant is 11.4, etc. [0007] Developing higher k dielectric materials as well as effective methods of using them to make microelectronic devices has been extremely challenging. One challenge has been the quality of the interface between a semiconductor wafer substrate (especially silicon wafer substrates) and the higher k dielectric material. Whereas silicon dioxide tends to provide an excellent electrical interface with semiconductor materials such as silicon, higher k dielectric materials tend to provide a lesser quality interface. The poor quality of the interface tends to impair the electrical performance of the resultant microelectronic in those instances in which a higher k dielectric material is deposited directly onto the silicon. [0008] It has been found by researchers that another dielectric material such as silicon dioxide or the like can provide a buffer, or bridge, between a semiconductor wafer and a high k dielectric material to improve electrical performance when using higher k dielectric materials. Generally, the buffer material is one that provides an electrical interface of a desired quality between the buffer and the semiconductor substrate, and the buffer in turn provides an electrical interface of a desired quality with the higher k dielectric material. [0009] The buffer layer should not be too thick or else the benefits of using a higher k dielectric material may be unduly reduced. Accordingly, it would be desirable to use a very thin layer (typically on the order of about 20 angstroms or less, preferably about 15 angstroms or less, more preferably about 10 angstroms or less) of another suitable bridging dielectric material such as silicon dioxide as such a buffer. As a representative, concrete example, assume it is desired to use a dielectric layer having electrical capacitance comparable to a 10 angstrom thick silicon dioxide layer. Two angstroms, e.g., of silicon dioxide can be used as a buffer. This leaves 8 angstroms of equivalent silicon dioxide still to be made up. This may be provided by using one or more materials with higher dielectric constant(s) that provide an equivalent electrical thickness with respect to silicon dioxide of 8 angstroms. The resultant dielectric system will then be thick enough generally to avoid undue quantum tunneling problems while still providing some electrical capacitance characteristics as if it were 10 angstroms of silicon dioxide. Additionally, the intervening buffer layer helps to ensure that the electrical couplings between the substrate and the buffer, and then the buffer to the higher k material pass muster. [0010] Of course, even though this example used a buffer layer having a thickness of 2 angstroms, other buffer thicknesses could be used depending upon factors such as the nature of the buffer material(s), the nature of the high k material(s), the desired electrical properties, thickness constraints, and the like. Thus, if the buffer layer were to be 6 angstroms thick, then only additional material that is the equivalent of 4 angstroms of silicon dioxide would need to be used to achieve the 10 angstrom standard used above as an illustration. Other standards, of course, may be used as well. Thus, one might desire to use a dielectric system that has the equivalent performance of 5 angstroms of silicon dioxide, or perhaps 15 angstroms of silicon dioxide, etc. [0011] Unfortunately, it has been very difficult to fabricate extremely thin silicon dioxide layers (e.g., those having a thickness below about 10 angstroms) with desired uniformity characteristics. Lack of uniformity can impair electrical properties of the resultant devices. Thus, maintaining uniformity is very desirable, especially when manufacturing devices with smaller features such as those devices whose gate dielectric layers are comprised of silicon dioxide and/or other dielectric materials and having an equivalent thickness of about 20 angstroms or less, preferably about 15 angstroms or less, and more preferably, about 10 angstroms or less of silicon dioxide. [0012] Thus, there is a strong need and desire in the industry to develop materials and/or methodologies that allow very thin, highly uniform dielectric layers to be formed with high precision. SUMMARY OF THE INVENTION [0013] As an overview, a substantially saturated, or saturated, oxide is chemically grown on a wafer, wherein the saturated thickness is greater than the desired thickness of the oxide. After the saturated oxide is formed, precision etching techniques are used to reduce the oxide thickness to the desired oxide thickness. The advantage of this approach is perhaps more appreciated in a concrete example. Assume that it is desired to form a silicon dioxide layer that is less than about 8 to 10 angstroms thick, e.g., less than a saturation oxide thickness when using desired oxide growing conditions and chemistry. Trying to form such an ultrathin layer directly, e.g., by growing the oxide and then trying to stop when growth reaches 6 angstroms, is difficult because too much thickness variation typically results. However, recognizing that saturated oxide is sufficiently uniform in thickness characteristics, and recognizing that precision, uniform etching of oxide is readily practiced to etch away angstroms, or fractions of angstroms, the present invention first grows an over-thick but uniform oxide layer by first forming a substantially saturated, or saturated oxide having a thickness on the order of 8 to 10 angstroms (which is typical for ozone or SC1 chemistry) and then uses precision etching techniques to etch back to the final desired thickness, e.g., 6 angstroms, or 5.5 angstroms, or 2 angstroms, etc. Such an approach allows very thin, highly uniform dielectric layers to be formed with high precision, e.g., a thickness uniformity that varies only by about +/-10%, more preferably about +/-5% when thickness is on the order of about 20 angstroms or less, preferably about 15 angstroms or less, more preferably about 10 angstroms or less. Meeting such uniformity standards becomes more difficult with decreasing layer thickness. For instance, a 20 angstrom layer with a uniformity of +/-5% can vary from 19 to 21 angstroms (a 2 angstrom range), but a 10 angstrom layer with a uniformity of +/-5% can vary only from 9.5 to 10.5 angstroms (1 angstrom range). [0014] For purposes of illustration, the invention will be described in an illustrative context of using ultrathin (e.g., less than about 20 angstroms, preferably less than 15 angstroms, more preferably less than about 10 angstroms) dielectric layers that constitute all or a portion of gate dielectric features. However, it should be readily appreciated that the invention is applicable to the formation of oxide films of any thickness in a wide range of uses with respect to microelectronic devices in general. Other representative applications include any feature or structure in which use of a thin, uniform oxide layer is desired. [0015] In one aspect of the present invention, a method of making an oxide layer, including the steps of forming a substantially saturated or saturated oxide layer directly or indirectly on a semiconductor surface of a semiconductor substrate, and etchingly reducing the thickness of the substantially saturated or saturated oxide layer by an amount such that the etched oxide layer has a thickness less than the substantially saturated or saturated oxide layer. In one preferred embodiment, the method further includes the step of depositing one or more high k dielectric material(s) directly or indirectly onto the etched oxide layer. In this one preferred aspect, the method can provide the gate dielectric layers of a gate dielectric component of a microelectronic device. [0016] In another aspect of the present invention, a method of making a dielectric, buffer layer, including the step of forming a dielectric buffer layer directly or indirectly on a semiconductor surface of a semiconductor substrate, wherein the buffer layer has a thickness in the range of from about 0.5 angstroms to about 20 angstroms. Preferably, the method further includes the step of depositing one or more high k dielectric materials directly or indirectly onto the buffer layer. In this preferred aspect the method can provide the gate dielectric layers of a gate dielectric component of a microelectronic device. [0017] In yet another aspect of the present invention, a microelectronic device including a gate dielectric layer formed directly or indirectly on a semiconductor surface of a semiconductor substrate, wherein the gate dielectric layer includes a buffer layer proximal to the substrate, the buffer layer having a thickness in the range of about 1 to about 10 angstroms and a uniformity of less than about +/-10%. [0018] In yet another aspect of the present invention, a manufacturing system used in the course of manufacturing a microelectronic device, including at least one processing chamber in which one or more semiconductor substrates are subjected to oxidizing and etching treatments, and program instructions to form an oxide layer, the instructions including oxidizing instructions that cause oxidizing to occur in a manner effective to form a saturated oxide layer directly or indirectly on one or more semiconductor surfaces of one or more semiconductor substrates positioned in a processing chamber, and etching instructions that cause etching to occur in a manner effective to etchingly reduce the thickness of the saturated oxide layer. In preferred embodiments, the program instructions cause oxidizing to occur in a manner effective to form an oxide layer having a thickness of less than about 20 angstroms, preferably less than about 10 angstroms. Also in preferred embodiments, the etching instructions cause etching to occur in a manner effective to etchingly reduce the thickness of the saturated oxide layer by an amount in the range from about 0.5 angstrom to about 19 angstroms, preferably in the range from about 1 angstrom to about 9 angstroms. [0019] In yet another aspect of the present invention, a method of making at least a portion of a gate dielectric layer, including the steps of: providing first information indicative of the thickness of a saturated or substantially saturated oxide layer; providing second information indicative of the etching characteristics of the saturated or substantially saturated oxide layer; and using the first and second information to formulate a process recipe for making at least a portion of the gate dielectric layer. In preferred embodiments, the at least a portion of the gate dielectric layer has a thickness of less than about 10 angstroms. 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