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  Control of priority and instruction rates on a multithreaded processorUSPTO Application #: 20070016757Title: Control of priority and instruction rates on a multithreaded processor Abstract: A method and apparatus for controlling issue rate of instructions for an instruction thread to be executed by a processor is provided. The rate at which instructions are to be executed for an instruction thread are stored and requests are issued to cause instructions to execute in response to the stored rate. The rate at which instruction requests are issued is reduced in response to instruction executions and is increased in the absence of instruction executions. In a multi-threaded processor, instruction rate is controlled by storing the average rate at which each thread should execute instructions. A value representative of the number of instructions available and not yet issued is monitored and is decreased in response to instruction executions. Execution of instructions is prevented on a thread if the number of instructions available but not yet issued falls below a defined value. A ranking order is assigned to a plurality of instructions threads for execution on a multi-threaded processor. A plurality of metrics related to the threads and required for establishment of the rank order are provided. Each metric is assigned to a set of bits and these are assembled in a composite metric being assigned to the most significant bits and the least important metric being assigned to the least significant bits. A ranking order is then assigned to the composite metrics in dependence on their values. (end of abstract) Agent: Flynn Thiel Boutell & Tanis, P.C. - Kalamazoo, MI, US Inventors: Adrian John Anderson, Martin John Woodhead USPTO Applicaton #: 20070016757 - Class: 712214000 (USPTO) Related Patent Categories: Electrical Computers And Digital Processing Systems: Processing Architectures And Instruction Processing (e.g., Processors), Instruction Issuing The Patent Description & Claims data below is from USPTO Patent Application 20070016757. Brief Patent Description - Full Patent Description - Patent Application Claims
[0001] This application is a division of U.S. Ser. No. 10/468 434, filed Sep. 21, 2004, which was the national stage of International Application No. PCT/GB2002/00742, filed Feb. 19, 2002, published in English, the disclosure of which is hereby incorporated by reference. [0002] This invention relates to the control of priorities and instruction issue rates on a multithreaded processor which is configured to process at any one time one of a number of different instruction threads. [0003] This invention is particularly beneficial when used with a system such as that described in our international patent application no. WO97/38372 the contents of which are incorporated herein by reference. This document discloses a processing system which is able to manage the processing of a number of different instruction threads by one or more data processors. This architecture looks repeatedly to the resources available and the instructions which have to be executed to determine which instruction thread should be processed on a following clock cycle. Such an architecture has many advantages in real time systems where the processor interacts with external devices such as hardware peripherals or other processors. In a real time system it is crucially important to ensure that all processing associated with an event is completed within a defined time. This is easy to verify for a processor which only performs one task but becomes very complex when the processor has many tasks to perform. In a system in which a processor has multiple threads it is quite possible to disturb the operation of a program running on one thread by changing the behaviour of a program running on different thread. This lack of thread conformity makes it difficult to develop programs which can execute reliably without prior knowledge of what is running on other threads. [0004] A conventional processor uses a priority system which permits urgent tasks to be handled more quickly than normal or non-urgent tasks. However, a processor which also has multiple hardware threads such as that described in WO97/38372 gives more flexibility than conventional processors and therefore requires a more flexible priority control. [0005] Preferred embodiments of the present invention seek to provide an issue rate control scheme for a multi threaded processor system. In particular, preferred embodiments seek to permit a program executing on one thread to control its use of processor resources in such a way that the processing requirements of both that program and any programs executing on other threads are met. In order to do this the program must be able to: define the rate at which its instructions are issued regardless of the behaviour of programs executed on other threads; handle an urgent event quickly whilst controlling any disruption to programs executed on other threads; and, adapt to disruptions in its defined rate of instruction issue caused by the handling of urgent events on other threads. [0006] The preferred embodiment is sufficiently robust to enable a thread to recover from processor overload in a reliable way, and to ensure that deviation from the defined bounds of execution rate on a thread can be detected. [0007] Furthermore it seeks to provide a control scheme that can operate at a number of levels of complexity whilst allowing a programmer to ignore aspects of the scheme that he does not require. [0008] A further embodiment seeks to minimise processor power consumption by clocking the processor at the minimum rate required to complete all its tasks. [0009] Preferred embodiments seek to assign ranked priorities to instruction threads to ensure the most effective use of processor resources. [0010] The invention is defined in the appended claims to which reference should now be made. [0011] A preferred embodiment of the invention will now be described in detail by way of example with reference to the accompanying drawings in which: [0012] FIG. 1 is a block diagram of the base architecture or a multithreaded processor system; [0013] FIG. 2 is a block diagram of the thread scheduling portion of the Media Control Core of FIG. 1; [0014] FIG. 3 is a block diagram of the thread ranking circuitry of FIG. 2; [0015] FIG. 4 is a block diagram of the issue request control circuitry of FIG. 2; [0016] FIG. 5 shows the arrangement of the deadline counter. [0017] The base architecture of the embodiment of the invention described here is shown in FIG. 1. The central part of this is a media control core (MCC) 2 which comprises a fine grained multithreaded processor. It has a plurality of inputs and outputs which can be coupled to real time data input and output devices 4 which may be, for example, video sources, audio sources, video outputs, audio outputs, data sources, storage devices, etc. In the most simple example only a single input and a single output will be provided. [0018] Also coupled to the MCC 2 are a plurality of data processing units 6. Each of these comprises a data processing core 8 which controls the processing of data via a data pipeline 10. The core 8 decodes and sequences micro instructions for the pipeline 10. [0019] Also coupled to the media control core 2 is a multibank cache memory 12 from which data may be retrieved by the MCC 2 and data processing unit 6 and into which data may be written by the MCC 2 and the data processing units 6. It includes temporary storage for data and instructions to be performed by the data processing cores on the input data and other internally generated data. These various sets of instructions will, when activated, comprise processing threads. [0020] The MCC 2 is a fine grained multithreading processing unit which directs data from inputs 4 to data processing cores 6 or to storage in cache 12 and provides data to outputs. It is arranged so that it may switch tasks on every clock cycle should this be required. To achieve this it checks on every clock cycle which possible operations it could perform by looking at the tasks to be performed and the resources available for those tasks to be performed. It also checks which of these tasks have the highest priority. More than one operation can commence on each clock cycle if sufficient processing power is provided. [0021] This resource checking ensures that everything required for a particular task to be performed is in place before an instruction is issued, including external resources such as data to an input port, or availability of data storage devices or outputs. It also includes the checking of internal resources such as registers for temporary storage, processing cores, or previously processed data required for a particular new processing operation. The MCC 2 operates to direct data from an input to an appropriate data processing unit 6 and for processing to take place routes appropriate instructions to the unit 6, and routes processed data to an output when required, making use of the cache as necessary. Once execution of a set of instructions is commenced on a processing unit the MCC 2 can look again at the various threads it can run and resources available for these whilst the program continues to run on the data processing unit. [0022] This resource and priority checking means that tasks which perform on real time data such as video input are able to be performed without the large memory buffers usually required for real time inputs. In e.g. video input, the MCC will look to see whether data is available at the IO port and if it is will receive that data and send it to either a portion of the multibanked cache or to data storage registers in preparation for processing by one of the data processing unit 6. [0023] Scheduling of the data processing unit 6 is under the control of MCC 2. For example, the data pipeline 10 of FIG. 1 will be made up of a number of processing elements such as multipliers, adders, shifters, etc, under the control of an associated data processing core 8 which runs a sequence of instructions retrieved from the cache to perform a data processing algorithm. Each of these processing cores has its own micro instruction ROM and/RAM storing sequences of instruction to perform a particular data process. The MCC 2 invokes the data processing unit 6 to perform its particular operation sequence by e.g. passing an address offset into its micro instruction ROM and instructing it to commence execution. It will then perform a particular process on either data from the multibank cache or on data passed from one of the inputs to the MCC 2 until it has completed, at which point it will signal to the MCC 2 that its processing is complete. [0024] In this embodiment of the present invention, the thread scheduling performed by the MCC 2 has two main elements. These are thread instruction issue rate control and thread priority. Instruction issue rate control allows the number of million instructions per second (MIPS) requested by each thread to be defined as a burst rate Bn. This allows the processor loading to be balanced so that each thread can operate independently of activity on other threads. So long as the total loading never exceeds the processor capacity, issue rate control is the only mechanism required to ensure that all the threads receive the processor resources they require. Continue reading... Full patent description for Control of priority and instruction rates on a multithreaded processor Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Control of priority and instruction rates on a multithreaded processor patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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