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Content addressable memory architectureContent addressable memory architecture description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20060239054, Content addressable memory architecture. Brief Patent Description - Full Patent Description - Patent Application Claims
RELATED APPLICATIONS [0001] This application is a continuation of U.S. application Ser. No. 10/912,768, filed Aug. 5, 2004, now U.S. Pat. No. 7,002,824, which is a continuation of U.S. application Ser. No. 10/234,033, filed Aug. 30, 2002, now U.S. Pat. No. 6,775,166. The entire teachings of the above applications are incorporated herein by reference. BACKGROUND OF THE INVENTION [0002] A Content Addressable Memory ("CAM") includes a plurality of CAM cells arranged in rows and columns. As is well-known in the art, a CAM cell can be dynamic memory based or static memory based and can be a binary cell or a ternary cell. A binary CAM cell has two possible logic states `1` and `0`. A ternary CAM cell has three possible logic states `0`, `1` and don't care (`X`) encoded in two bits. [0003] A search and compare feature allows all of the CAM cells in the CAM to be searched for an entry with data that matches a search key. An entry can include a plurality of CAM cells. For example, a 72-ternary bit entry includes 72 ternary CAM cells. If an entry matching the search key is stored in the CAM, the address of the matching entry, that is, the match address, a match flag indicating whether there is a match and a multiple match flag indicating whether there are more than one match are typically provided. The match address may be used to find data associated with the search key stored in a separate memory in a location specified by the match address. [0004] Each entry in the CAM has an associated match line coupled to each CAM cell in the entry. Upon completion of the search, the state of the match line for the entry indicates whether the entry matches the search key. The match lines from all entries in the CAM are provided to a match line detection circuit to determine if there is a matching entry for the search key in the CAM and then the result of the match line detection circuit is provided to a priority encoder. The priority encoder selects the match entry with the highest priority if there are a plurality of match entries for the search key in the CAM. The priority encoder also provides the match address and a match flag. The match flag is enabled when there is at least one match/hit. [0005] Typically, a CAM with a large number of CAM cells is subdivided into a plurality of banks. FIG. 1 illustrates a simplified prior art CAM 100 subdivided into a plurality of banks 102A-D, with each bank including entries comprising a plurality of CAM cells (not shown) and a supporting circuit (not shown) for the bank. Search data 104 for a search and compare operation is received at external pins of the CAM 100, routed to the center of the CAM, then routed from the center to each of the banks. The path from the external search data pin to bank 0 102a is shown as trace 106. A search for a matching entry for the search data is performed in parallel in each bank 102A-D. Upon completing a search operation for search data, each bank performs operations including priority encoding to select the match address for the highest priority matching entry stored in the respective bank. The result of the search in each bank is collected by the CAM output logic circuit 108. The CAM output logic circuit 108 is located in the center of the CAM 100. A priority encoder in the CAM output logic circuit 108 selects the highest priority matching entry from the result of the search in each bank, adds a bank identifier to the matching entry and outputs the match address 110 for the highest priority matching entry for the search word and a match flag. The operation of a priority encoder has been described but operations for other output results typically provided by a CAM such as, a match flag and a multiple match flag are also operative as known by those skilled in the art. SUMMARY OF THE INVENTION [0006] As described above, search data is routed to the center from external pins, then routed to each bank. After performing an operation, the result data from each bank is returned to the center. In order to support the result data and search data paths, all connecting traces are concentrated in the center, thereby making the center area bigger and distances between each bank wider. Therefore area efficiency of silicon is decreased because the center area must be reserved for the connecting traces and supporting circuit. [0007] Routing congestion is avoided by replacing the plurality of banks with an array of sub-blocks. All of the data is input on one side of the array of sub-blocks and routed across each row of the array. Results are output on the opposite side of the array to the input data. The issue of latency is addressed with an optional pipeline stage in each sub-block. All of the pipeline stages are enabled resulting in higher latency when operating at a high clock speed. When the array is operated at a lower clock speed, some or all of the pipe stages can be bypassed and latency reduced. [0008] Instead of routing all data lines and result lines to the center of the CAM, the present invention arranges data lines across each row of sub-blocks and forwards the result of a search of each sub-block to the next subsequent sub-block in the row. The results of the search in each row of sub-blocks are coupled to a priority encoder to select the match address for the highest priority matching entry stored in a matching entry in a sub-block in the array. [0009] A Content Addressable Memory includes a plurality of data inputs for receiving data, an array of content addressable sub-blocks and a plurality of outputs for the results of operations in rows of sub-blocks in the array. The plurality of outputs are located on the side of the array opposite to the data inputs. Each sub-block in a first column of the array is coupled to the plurality of data inputs. Data received by a sub-block in a row in the first column of the array is propagated across the array to each subsequent sub-block in the row of the array. The Content Addressable Memory also includes priority encoder logic coupled to each sub-block in a last column in the array for selecting a highest priority row match output for the result of a search and compare operation. The priority encoder logic also provides a match flag and a match address corresponding to the selected highest priority matching entry. [0010] Each sub-block comprises a plurality of cell arrays. The received data includes search data and each sub-block performs a search for a match for the search data stored in the plurality of cell arrays. Each sub-block in a row forwards a match flag and a sub-block match address dependent on the result of the search in the sub-block and the result of searches in all previous sub-blocks in the row to the next sub-block in the row. [0011] Each sub-block in a row is coupled to a next sub-block in a subsequent column for forwarding received data and results to the next subsequent sub-block. Entries with highest priority may be stored in sub-blocks in the first column. A match in a sub-block in a previous column overrides a match in a sub-block in a subsequent column. Each sub-block may include a pipeline stage for latching the received data and the operation results prior to forwarding the received data to the next sub-block in the row. The pipeline stage may be enabled to increase latency or bypassed to decrease latency. [0012] The number of columns in the array may be four and the number of rows in the array may be 32 or 16. Each cell array may include a plurality of dynamic random access memory based cells or static random access memory based cells. The cell may be ternary or binary. The operation may be a read, write or search and compare. BRIEF DESCRIPTION OF THE DRAWINGS [0013] The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings in which like reference characters refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention. [0014] FIG. 1 illustrates a simplified prior art CAM subdivided into a plurality of banks, with each bank including entries comprising a plurality of CAM cells; [0015] FIG. 2A illustrates data paths and search result paths in a CAM including an array of content addressable sub-blocks according to the principles of the present invention; [0016] FIG. 2B illustrates one priority assignment for sub-blocks in the CAM; [0017] FIG. 3 is a block diagram of one of the sub-blocks in the CAM array shown in FIG. 2A; [0018] FIG. 4 is a block diagram of one of the cell arrays in the sub-block shown in FIG. 3; [0019] FIG. 5 is a block diagram of one embodiment of the CAM cell shown in FIG. 4; [0020] FIG. 6 is a cross-section through the sub-block shown in FIG. 3 illustrating the forwarding of one of the received data bits through the sub-block; Continue reading about Content addressable memory architecture... Full patent description for Content addressable memory architecture Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Content addressable memory architecture patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Content addressable memory architecture or other areas of interest. ### Previous Patent Application: On-die offset reference circuit block Next Patent Application: Self-aanalyzing memory word Industry Class: Static information storage and retrieval ### FreshPatents.com Support Thank you for viewing the Content addressable memory architecture patent info. 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