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  Configurable mapping of devices to bus functionsUSPTO Application #: 20060161692Title: Configurable mapping of devices to bus functions Abstract: Techniques are disclosed for enabling a single computer system to execute both operating systems that permit multiple devices to be mapped to a single PCI function and operating systems that do not permit such mapping. Prior to loading and executing an operating system (e.g., during system reset), the computer system determines whether the operating system supports mapping of multiple devices to a single function. If such mapping is supported, the computer system maps multiple devices on a single PCI card to a single function in the PCI configuration space for the card. If such mapping is not supported, the computer system maps each device to a separate PCI function. The computer system then loads and executes the operating system. The operating system is thereby enabled to access all devices on the bus according to the particular device-function mapping scheme supported by the operating system. (end of abstract)
Agent: Hewlett-packard Company Intellectual Property Administration - Ft. Collins, CO, US Inventor: Daniel V. Zilavy USPTO Applicaton #: 20060161692 - Class: 710008000 (USPTO) Related Patent Categories: Electrical Computers And Digital Data Processing Systems: Input/output, Input/output Data Processing, Peripheral Configuration The Patent Description & Claims data below is from USPTO Patent Application 20060161692. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This application is a divisional application of commonly-owned U.S. patent application Ser. No. 10/644,291, filed on Aug. 20, 2003, entitled "Configurable Mapping of Devices to Bus Functions". BACKGROUND [0002] 1. Field of the Invention [0003] The present invention relates to communications buses for use in computer systems and, more particularly, to techniques for efficiently configuring multiple devices connected to a communications bus. [0004] 2. Related Art [0005] A conventional computer system typically includes a central processing unit (CPU), main memory, and a number of devices that are in communication with each other and the CPU over a data bus, also referred to as an Input/Qutput (I/O) bus. The CPU, for example, transmits commands and data to the devices (such as hard disk drives, printers, and displays) over the data bus, and vice versa. A variety of conventional data buses exist, such as the Small Computer System Interface (SCSI) bus, the Industry Standard Architecture (ISA) bus, the Peripheral Component Interface (PCI) bus, and the Inter-IC (I.sup.2C) bus. A conventional computer system also typically includes a system bus that transports data between the processor and the main memory. [0006] Referring to FIG. 1, a block diagram is shown of a prior art computer system 100. The computer system includes a central processing unit (CPU) 102 and main memory 104 (e.g., RAM) coupled to a system bus 106. The system 100 also includes a PCI bus 110, which is coupled to the system bus 106 by a system-to-PCI bridge 108. Four cards 114a-c (also referred to herein as "physical PCI devices") are coupled to the PCI bus 110. As described in more detail below, each of the cards 114a-c may implement one or more "logical" PCI devices. In the example shown in FIG. 1, card 114a implements two logical devices 112a-b, card 114b implements one logical device 112c, and card 114c implements one logical device 112d. [0007] Both logical devices 112a and 112b may, for example, be UARTs (universal asynchronous receiver-transmitters). A UART is a computer component that handles asynchronous serial communication. Every computer contains at least one UART to manage its serial ports, and some internal modems have their own UART. In particular, both devices 112a-b may be implemented using a single processor on the card 114a having the ability to function as two UARTs, or using two separate sets of components on the card 114a. [0008] The CPU 102 and main memory 104 may communicate with each other over the system bus 106, the devices 112a-d may communicate with each other over the PCI bus 110, and the CPU 102 and main memory 104 may communicate with the devices 112a-d through the system bus 106 and PCI bus 110 over the system-to-PCI bridge 108. [0009] The PCI bus 110 provides a "configuration space," currently defined by the PCI Local Bus Specification Revision 2.3, that is used to store configuration information for devices coupled to the bus 110 (e.g., devices 112a-d in the example illustrated in FIG. 1). The configuration space for each PCI device contains configuration information such as a device identifier, vendor identifier, and revision identifier. The configuration information for a particular PCI device typically is stored in an EEPROM on the PCI card and is then loaded into registers from which it may be accessed (e.g., by initialization software and error handling software) to obtain information about the device and to configure the device to function properly in a particular system. [0010] More specifically, referring to FIG. 2, a diagram is shown of an example PCI configuration space 200 is illustrated as a single contiguous set of configuration registers that are allocated to PCI buses and to devices on such buses in a manner that will now be described in more detail. [0011] Each PCI bus within a computer system is allocated a portion of the configuration space 200. In the example shown in FIG. 2, the configuration space 200 is divided into three sub-spaces 202a-c, each of which is allocated to one PCI bus. Each of the bus configuration spaces 202a-c includes 64K of memory. The system 100 shown in FIG. 1 only includes one PCI bus 110, which would therefore be allocated the first portion 202a of the configuration space 200. The portion 202a is therefore referred to herein as a "bus configuration space." [0012] As further shown in FIG. 2, each of the bus configuration spaces 202a-c is further subdivided into 32 sub-spaces, each of which is 2K long and which may be allocated to a separate physical device (e.g., card) on the corresponding PCI bus. Each of these 2K sub-spaces is therefore referred to herein as a "physical device configuration space." Referring again to FIG. 1, the computer system 100 includes three physical PCI devices 114a-c. PCI device 114a may, for example, be allocated physical device configuration space 204a, PCI device 114b may be allocated physical device configuration space 204b, and PCI device 114c may be allocated physical device configuration space 204c. [0013] The PCI bus architecture allows devices that perform more than one function to be connected to a PCI bus. An example of a device that performs more than one function is a multi-port device, such as a device having two SCSI ports on a single chip. Another example is device 114a, which implements the functionality of two UARTs in logical devices 112a and 112b, respectively. A separate configuration space is allocated to each function (e.g., port or UART) in a multifunction device. More specifically, each physical device configuration space is divided into eight "function configuration spaces," each of which contains configuration registers for a particular function. [0014] For example, referring to FIG. 3, a diagram is shown of the physical device configuration space 204a which, in the present example, is allocated to physical device 114a. The physical device configuration space 204a is subdivided into eight 256-byte "function configuration spaces" 300a-h. Each of the function configuration spaces 300a-h is designed to store configuration information for a distinct function (e.g., port or UART) of the corresponding physical device 114a. [0015] Physical PCI devices are only required to implement a single function. A single-function device may, for example, provide configuration information for its single function in the first of its function configuration spaces, and leave the remaining function configuration spaces that are allocated to it empty. A multi-function device may store configuration information in two or more of its function configuration spaces, up to a maximum of eight functions. [0016] Referring to FIG. 4, the function configuration space 300a (corresponding to function 0 of PCI device 114a in the present example) is shown in more detail. The function configuration space 300a includes both a 64-byte header portion 402 and a 192-byte configuration register portion 404. [0017] Referring to FIG. 5, a diagram is shown which illustrates the header portion 402 of function configuration space 300a in more detail. The header portion 402 is illustrated in FIG. 5 as a two-dimensional array that is 32 bits (4 bytes) wide and 16 bytes long. As defined by the PCI specification, header portion 402 includes the following fields: device identifier (ID) 502a, vendor ID 502b, status 502c, command 502d, class code 502e, revision ID 502f, BIST (built-in self test) 502g, header type 502h, latency timer 502i, cache line size 502j, base address registers 502k, CardBus CIS Pointer 502l, subsystem ID 502m, subsystem vendor ID 502n, expansion ROM base address 502o, reserved 502p, capabilities pointer 502q, reserved 502r, Max_Lat 502s, Min_Gnt 502t, interrupt pin 502u, and interrupt line 502v. The fields that are not discussed in detail herein are well-known to those of ordinary skill in the art and are described in more detail in the PCI specification. [0018] Some operating systems, such as HP-UX version 11i and higher, allow multiple logical devices on a single PCI card to be allocated (mapped) to a single PCI function. For example, as mentioned above, the logical devices 112a and 112b in the system 100 (FIG. 1) may be implemented on the single PCI card 114a. Logical devices 112a and 112b may, therefore, be mapped to the single function 300a (FIG. 3) if the system 100 operates using an operating system, such as the HP-UX operating system, which allows mapping of multiple devices to a single PCI function. The ability to map multiple devices (such as UARTs) to a single function makes the use of functions more efficient, because the registers in only one function need be configured and maintained to provide configuration information for two devices. [0019] One way to map multiple devices to a single PCI function is as follows. A special subsystem ID value may be designated by the operating system (e.g., HP-UX) to means that "multiple devices are mapped to this function." This special device ID value will be referred to herein by the label MULT_DEVICES. To map two or more devices (such as devices 112a and 112b) implemented on a single PCI card to a single PCI function in the card's physical device configuration space, the value MULT_DEVICES may be stored in the subsystem ID field 502m (FIG. 5) of the function. The two devices then share the configuration registers 404, with the registers allocated to the two devices being contiguous within the configuration registers 404. [0020] Assume that both devices 112a and 112b have been mapped to the single function 300a, and that both devices 112a and 112b therefore share the single configuration space header 402. Logical devices on a PCI bus are addressed by a combination of bus number, device number (ID), and function number. When a component of the system 100, such as device 112c, attempts to access function 402 by addressing the function at bus zero, device number MULT_DEVICES, and function zero, the operating system will interpret the device number of MULT_DEVICES as a special value which indicates that two devices are mapped to the function being addressed. The operating system is configured to access the configuration registers 404 for the devices 112a-b appropriately in response to this special address. [0021] Other operating systems, such as Microsoft.RTM. .NET, however, may not provide the ability to map multiple devices to a single PCI function and may not be able to correctly interpret the meaning of the special subsystem ID value of MULT_DEVICES. If such an operating system is loaded onto the system 100, therefore, the operating system may not recognize and therefore be unable to access the second mapped device (e.g., device 112b). [0022] One way to attempt to solve this problem would be to re-map each of the devices 112a-d to a separate PCI function. After performing this re-mapping, operating systems such as Microsoft.RTM. NET would be able to access all of the devices 112a-d correctly. Such a re-mapping might, however, make other operating systems, such as HP-UX, unable to access all of the devices 112a-d correctly. Attempting to solve this problem by modifying one or more of the operating systems themselves would be costly and time-consuming and would require customers to upgrade their operating systems. Continue reading... Full patent description for Configurable mapping of devices to bus functions Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Configurable mapping of devices to bus functions patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. 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