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  Configurable computing machine and related systems and methodsUSPTO Application #: 20060101250Title: Configurable computing machine and related systems and methods Abstract: A computing machine includes programmable integrated circuits, a configuration registry, and a processor. The registry stores a file that defines a circuit having portions, and the processor is, in response to the file, operable to instantiate one of the circuit portions on one of the programmable integrated circuits. Consequently, by accessing a file that defines a circuit, such a computing machine can often instantiate the circuit on a pipeline accelerator regardless of the hardware that compose the accelerator and despite modifications to the circuit or to the hardware. That is, the computing machine can often “fit” the circuit into the pipeline accelerator regardless of its composition. (end of abstract) Agent: Graybeal Jackson Haley LLP - Bellevue, WA, US Inventors: John Rapp, Chandan Mathur, Scott Hellenbach, Mark Jones, Joseph A. Capizzi USPTO Applicaton #: 20060101250 - Class: 712226000 (USPTO) Related Patent Categories: Electrical Computers And Digital Processing Systems: Processing Architectures And Instruction Processing (e.g., Processors), Processing Control, Instruction Modification Based On Condition The Patent Description & Claims data below is from USPTO Patent Application 20060101250. Brief Patent Description - Full Patent Description - Patent Application Claims
CLAIM OF PRIORITY [0001] This application claims priority to U.S. Provisional Application Ser. Nos. 60/615,192, 60/615,157, 60/615,170, 60/615,158, 60/615,193, and 60/615,050, filed on Oct. 1, 2004, which are incorporated by reference. CROSS REFERENCE TO RELATED APPLICATIONS [0002] This application is related to U.S. patent application Ser. Nos. ______ (Attorney Docket Nos. 1934-21-3, 1934-23-3, 1934-24-3, 1934-26-3, 1934-31-3, 1934-35-3, and 1934-36-3), which have a common filing date and assignee and which are incorporated by reference. BACKGROUND [0003] A peer-vector computing machine, which is described in the following U.S. Patent Publications, includes a pipeline accelerator that can often perform mathematical computations ten to one hundred times faster than a conventional processor-based computing machine can perform these computations: 2004/0133763; 2004/0181621; 2004/0136241; 2004/0170070; and, 2004/0130927, which are incorporated herein by reference. The pipeline accelerator can often perform mathematical computations faster than a processor because unlike a processor, the accelerator processes data in a pipelined fashion while executing few, if any, software instructions. [0004] Unfortunately, despite its oft-superior data-processing speed, a peer-vector computing machine may lack some of the popular features of a conventional processor-based computing machine. [0005] For example, a peer-vector computing machine may lack the ability to configure itself to operate with the installed hardware that composes the pipeline accelerator; and may lack the ability to reconfigure itself in response to a change in this hardware. [0006] Typically, a conventional processor-based computing machine can configure its software and settings during its start-up routine to operate with the hardware installed in the machine, and can also reconfigure its software and settings in response to a change in this hardware. For example, assume that while the processor-based machine is "off", one increases the amount of the machine's random-access memory (RAM). During the next start-up routine, the machine detects the additional RAM, and reconfigures its operating system to recognize and exploit the additional RAM during subsequent operations. Similarly, assume that one adds a wireless-router card to the bus while the processor-based machine is off. During the next start-up routine, the machine detects the card and configures its operating system to recognize and allow a software application such as a web browser to use the card (the machine may need to download the card's driver via a CD-ROM or the internet). Consequently, to install new hardware in a typical processor-based machine, an operator merely inserts the hardware into the machine, which then configures or reconfigures the machine's software and settings without additional operator input. [0007] But a peer-vector machine may lack the ability to configure or reconfigure itself to operate the hardware that composes the pipeline accelerator. For example, assume that one wants the peer-vector machine to instantiate a pre-designed circuit on multiple programmable-logic integrated circuits (PLICs) such as field-programmable gate arrays (FPGAs), each of which is disposed on a respective pipeline unit of the pipeline accelerator. Typically, one manually generates configuration-firmware files for each of the PLICs, and loads these files into the machine's configuration memory. During a start-up routine, the peer-vector machine causes each of the PLICs to download a respective one of these files. Once the PLICs have downloaded these firmware files, the circuit is instantiated on the PLICs. But if one modifies the circuit, or modifies the type or number of pipeline units in the pipeline accelerator, then he may need to manually generate new configuration-firmware files and load them into the configuration memory before the machine can instantiate the modified circuit on the pipeline accelerator. [0008] Furthermore, the peer-vector computing machine may lack the ability to continue operating if a component of the machine fails. [0009] Some conventional processor-based computing machines have redundant components that allow a machine to be fault tolerant, i.e., to continue operating when a component fails or otherwise exhibits a fault or causes a fault in the machine's operation. For example, a multi-processor-based computing machine may include a redundant processor that can "take over" for one of main processors if and when a main processor fails. [0010] But unfortunately, a peer-vector machine may have a lower level of fault tolerance than a fault-tolerant processor-based machine. [0011] Moreover, existing fault-tolerant techniques may add significant cost and complexity to a computing machine. Per the above example, assume that a processor-based computing machine includes a redundant processor. If the machine has only one main processor, then adding the redundant processor may double the area that the processors occupy, and may double the costs for procuring and maintaining the processors. [0012] Therefore, a need has arisen for a peer-vector computing machine that can configure itself to operate with the hardware that composes the pipeline accelerator, and that can reconfigure itself to recognize and operate with newly modified accelerator installed hardware. [0013] A need has also arisen for a peer-vector machine having a higher level of fault tolerance. [0014] Furthermore, a need has arisen for a fault-tolerant technique that is less costly and complex than providing redundancy solely by the inclusion of dedicated redundant components. SUMMARY [0015] According to an embodiment of the invention, a computing machine includes programmable integrated circuits, a configuration registry, and a processor. The registry stores a file that defines a circuit having portions, and the processor is, in response to the file, operable to instantiate one of the circuit portions on one of the programmable integrated circuits. [0016] Consequently, by accessing a file that defines a circuit, such a computing machine can often instantiate the circuit on a pipeline accelerator regardless of the hardware that composes the accelerator and despite modifications to the circuit or to the hardware. That is, the computing machine can often "fit" the circuit into the pipeline accelerator regardless of its composition. BRIEF DESCRIPTION OF THE DRAWINGS [0017] FIG. 1 is a schematic block diagram of a peer-vector computing machine according to an embodiment of the invention. [0018] FIG. 2 is a schematic block diagram of a pipeline unit from the pipelined accelerator of FIG. 1 and including a PLIC according to an embodiment of the invention. [0019] FIG. 3 is a block diagram of the circuitry that composes the interface-adapter and framework-services layers of the PLIC of FIG. 2 according to an embodiment of the invention. Continue reading... Full patent description for Configurable computing machine and related systems and methods Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Configurable computing machine and related systems and methods patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Configurable computing machine and related systems and methods or other areas of interest. ### Previous Patent Application: Arrangements for adaptive response to latencies Next Patent Application: System and method for simultaneously executing multiple conditional execution instruction groups Industry Class: Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) ### FreshPatents.com Support Thank you for viewing the Configurable computing machine and related systems and methods patent info. IP-related news and info Results in 0.44478 seconds Other interesting Feshpatents.com categories: Canon USA , Celera Genomics , Cephalon, Inc. , Cingular Wireless , Clorox , Colgate-Palmolive , Corning , Cymer , |
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