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  Computer-based tool and method for designing an electronic circuit and related systemUSPTO Application #: 20060230377Title: Computer-based tool and method for designing an electronic circuit and related system Abstract: A computer-based circuit-design tool includes a front end, an interpreter coupled to the front end, and a generator coupled the interpreter. The front end receives symbols that define an algorithm, and the interpreter parses the algorithm into respective algorithm portions. The generator identifies a corresponding circuit template for each of the algorithm portions, each template defining a circuit for executing the respective algorithm portion, and interconnects the identified templates such that the interconnected templates define a circuit that is operable to execute the algorithm. As compared to prior design tools, this tool may decrease the time and effort required to design a circuit for instantiation on a programmable logic integrated circuit (PLIC) or on an application-specific integrated circuit (ASIC) by allowing one to construct the circuit from previously written templates that define previously tested and debugged circuits. (end of abstract)
Agent: Graybeal Jackson Haley LLP - Bellevue, WA, US Inventors: John Rapp, Scott Hellenbach, T. J. Kurian, D. James Schooley, Troy Cherasaro USPTO Applicaton #: 20060230377 - Class: 716018000 (USPTO) Related Patent Categories: Data Processing: Design And Analysis Of Circuit Or Semiconductor Mask, Circuit Design, Logical Circuit Synthesizer The Patent Description & Claims data below is from USPTO Patent Application 20060230377. Brief Patent Description - Full Patent Description - Patent Application Claims
CLAIM OF PRIORITY [0001] This application claims priority to U.S. Provisional Application Ser. Nos. 60/615,192, 60/615,157, 60/615,170, 60/615,158, 60/615,193, and 60/615,050, filed on Oct. 1, 2004, which are incorporated by reference. CROSS REFERENCE TO RELATED APPLICATIONS [0002] This application is related to U.S. patent application Ser. Nos. ______ (Attorney Docket Nos. 1934-21-3,1934-24-3, 1934-25-3, 1934-26-3,1934-31-3, 1934-35-3, and 1934-36-3), which have a common filing date and assignee and which are incorporated by reference. BACKGROUND [0003] Electronics engineers often instantiate circuits, such as logic circuits, on programmable logic integrated circuits (PLICs) such as field-programmable gate arrays (FPGAs), and on application-specific integrated circuits (ASICs). Because an engineer typically configures with firmware the circuit components and interconnections inside of a PLIC, he can modify a circuit instantiated on the PLIC merely by modifying and reloading the firmware. An example of a computer architecture that exploits the ability to configure and reconfigure circuitry within a PLIC with firmware is described in U.S. Patent Publication No. 2004/0133763, which is incorporated herein by reference. [0004] But unfortunately, it is often difficult and time consuming to design a circuit for instantiation on a PLIC, and an increase in the level of design difficulty and the time required to complete the design often accompany the routing resources, component density, and component variety on a PLIC. [0005] Comparatively, when a software programmer writes source code for a software application, he can often save time by incorporating into the application previously written and debugged software objects from a software-object library. Suppose the programmer wishes to write a software application that solves for y in the following equation: y=x.sup.2+z.sup.3 (1) Further suppose that a software-object library includes a first software object for squaring a value (here x), a second software object for cubing a value (here z), and a third software object for summing two values (here x.sup.2 and z.sup.3). By incorporating pointers to these three objects in the source code, a compiler effectively merges these objects into the software application while compiling the source code. Therefore, the object library allows the programmer to write the software application in a shorter time and with less effort because the programmer does not have to "reinvent the wheel" by writing and debugging pieces of source code that respectively square x, cube z, and sum x.sup.2 and z.sup.3. Furthermore, if the programmer needs to modify the software application, he can do so without modifying and re-debugging the first, second, and third software objects. [0006] In contrast, there are typically no time- or effort-saving equivalents of software objects available to a hardware engineer who wishes to design a circuit for instantiation on a PLIC; consequently, when a hardware engineer designs a circuit for instantiation on a PLIC, he typically must write the source code (e.g., Verilog Hardware Description Language (VHDL)) "from scratch." Suppose that an engineer wishes to design a logic circuit that solves for y equation (1). Because there are typically no hardware equivalents of the first, second, and third software objects described in the preceding paragraph, the engineer may write source code that describes first and second portions of a circuit for solving equation (1). The first circuit portion squares x, cubes z, and sums x.sup.2 and z.sup.3, and the second circuit portion interfaces the first circuit portion to the external pins of the PLIC. The engineer then compiles the source code with PLIC design tool (typically provided by the PLIC manufacturer), which synthesizes and routes the circuit and then generates the configuration firmware that, when loaded into the PLIC, instantiates the circuit. Next, the engineer loads the firmware into the PLIC and debugs the instantiated circuit. Unfortunately, the synthesizing and routing steps are often not trivial, and may take a number of hours or even days depending upon the size and complexity of the circuit. And even if the engineer makes only a minor modification to a small portion of the circuit, he typically must repeat the synthesizing, routing, and debugging steps for the entire circuit. [0007] Another factor that may add to the time and effort that an engineer expends while designing a circuit for instantiation on a PLIC is that a PLIC design tool typically recognizes only hardware-specific source code. Suppose that a mathematician, who writes an equation using mathematical symbols (e.g., "+," "-," ".ltoreq.," ".SIGMA.," ".intg." ".differential.," "x.sup.2," "z.sup.3," and " "), wishes to instantiate on a PLIC a circuit that solves for a variable in a complex equation that includes, e.g., partial derivatives and integrations. Because a PLIC design tool typically recognizes few, if any, mathematical symbols, the mathematician often must explain the equation and the desired operating parameters (e.g., latency and precision) of the circuit to a hardware engineer, who then translates the equation and operating parameters into source code that the design tool recognizes. These explanation and translation steps are often time consuming and difficult for the engineer, particularly where the equation is mathematically complex or the circuit has stringent operating parameters (e.g., high speed, high precision). [0008] Therefore, a need has arisen for a new methodology and for a new tool for designing a circuit for instantiation on a PLIC. SUMMARY [0009] According to an embodiment of the invention, a computer-based circuit design tool includes a front end, an interpreter coupled to the front end, and an integrator coupled to the interpreter. The front end receives symbols that define a logical expression, and the interpreter parses the expression into respective portions. The integrator identifies a corresponding circuit template for each of the expression portions, and logically interconnects the identified templates into a representation of an electronic circuit that is operable to execute the expression. [0010] As compared to prior circuit design tools, such a tool may shorten the time and reduce the effort that an engineer expends designing a circuit for instantiation on a PLIC by allowing the engineer to build the circuit from templates of previously designed and debugged circuits. [0011] According to a related embodiment of the invention, the front end of the design tool recognizes mathematical symbols so that one can design a PLIC circuit for executing a mathematical expression with little or no assistance from a hardware engineer. BRIEF DESCRIPTION OF THE DRAWINGS [0012] FIG. 1 is a block diagram of a peer-vector computing machine having a pipelined accelerator that one can design with a design tool according to an embodiment of the invention. [0013] FIG. 2 is a block diagram of a pipeline unit that includes a PLIC and that can be included in the pipelined accelerator of FIG. 1 according to an embodiment of the invention. [0014] FIG. 3 is a diagram of the circuit layers that compose the hardware interface layer within the PLIC of FIG. 2 according to an embodiment of the invention. [0015] FIG. 4 is a block diagram of the circuitry that composes the interface adapter and framework services layers of FIG. 3 according to an embodiment of the invention. [0016] FIG. 5 is a diagram of a hardware-description file for a circuit that one can instantiate on a PLIC according to an embodiment of the invention. [0017] FIG. 6 is a block diagram of a PLIC circuit-template library according to an embodiment of the invention. [0018] FIG. 7 is a block diagram of circuit-design system that includes a computer-based tool for designing a circuit using templates from the library of FIG. 6 according to an embodiment of the invention. [0019] FIG. 8 illustrates the parsing of a mathematical expression according to an embodiment of the invention. Continue reading... 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