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Compression of emulation trace dataRelated Patent Categories: Data Processing: Structural Design, Modeling, Simulation, And Emulation, EmulationCompression of emulation trace data description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070083353, Compression of emulation trace data. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS REFERENCE TO RELATED APPLICATION [0001] This application is a divisional of prior U.S. application Ser. No. 10/454,818, filed Jun. 5, 2003, the entire contents of which are incorporated herein by reference. FIELD OF THE INVENTION [0002] Aspects of the present invention are directed generally to methods and apparatuses for handling trace data from an emulation system, and more particularly to compression of such trace data to a more manageable size. BACKGROUND [0003] Emulation systems typically include one or more integrated circuit chips, each of which emulates a portion of a digital design. The integrated circuit chips may be field-programmable devices (FPDs) such as field-programmable gate arrays (FPGAs). Each FPD includes a set of reconfigurable logic blocks (RLBs) interconnected by a programmable routing resource matrix. The typical FPGA has up to a few tens of thousands of usable RLBs. Design state elements, such as logic gates, are mapped onto the RLBs such that the typical FPGA may emulate up to several hundred thousand design logic gates. [0004] During emulation of a design in an FPD, it is desirable to obtain trace data of the states of the various design state elements and/or other design elements and/or design signals mapped onto the emulation FPD. Such trace data, also known as user visibility data, is made available to the user and is often used to debug a design. Unfortunately, as the number of state elements mapped into an FPD increases, the amount of trace data increases as well. For example, an FPGA emulating one hundred thousand state elements would generate up to one hundred thousand bits, or 0.1 Mb, of trace data per clock cycle. This trace data is further increased where emulation systems incorporate a number of parallel FPGAs. For instance, a system having ten parallel FPGAs would generate up to 1 Mb of trace data per clock cycle. [0005] The amount of trace data to be dealt with is dramatically increased when one considers that emulation runs typically involve a plurality of clock cycles, such as hundreds of millions of clock cycles or more. For example, where an emulation is run over one billion clock cycles, the total amount of trace data generated during the emulation may be up to (1 billion).times.1Mb=1,000 terabits (Tb). Thus, there becomes the problem of how to store, transfer, and/or otherwise handle all of this trace data. Although the cost of memory has decreased over the years, it is nevertheless expensive. Large amounts of memory also takes up valuable real estate and requires additional power, both of which are usually of limited availability in an emulation system. It would therefore be desirable to limit the amount of memory in an emulation system. [0006] Yet another complication arises when one considers the speed at which the emulation clock runs. Typical emulation systems may run a clock at 1 MHz or more. For example, where the clock in the above example is run at 1 MHz, the total bandwidth of trace data generated may be up to (1 Mb).times.(1 MHz)=1 Tb per second. When an emulation system is run over multiple emulation clock cycles, the bandwidth of trace data often exceeds the capabilities of state-of-the-art physical interfaces, such as integrated circuit packaging pin limitations, memory chip size, and network bandwidth. SUMMARY OF THE INVENTION [0007] There is therefore a need for an emulation system that can provide useful quantities of trace data without requiring unreasonable trace data transfer bandwidth requirements and/or data storage requirements. Thus, according to one aspect of the present invention, some or all of the trace data from an emulation system may be compressed. Any suitable data compression algorithm may be used without departing from the scope of the invention. Such compression may occur prior to or after storage. [0008] According to a further aspect of the present invention, scan chains may be implemented to receive trace data from configurable logic blocks inside one or more emulation chips, and the data received from the scan chains may be compressed. Where delta compression is used, the scan chains may also perform a delta detection function. Alternatively, delta detection may be performed using the outputs of the scan chains. In addition, one or more detectors may be implemented within or outside of the scan chains. [0009] According to still another aspect of the present invention, compression of the trace data may include receiving a plurality of data sets and performing compression along cross-sections of the combined data sets. [0010] These and other features of the invention will be apparent upon consideration of the following detailed description of illustrative embodiments. BRIEF DESCRIPTION OF THE DRAWINGS [0011] The foregoing summary of the invention, as well as the following detailed description of illustrative embodiments, is better understood when read in conjunction with the accompanying drawings, which are included by way of example, and not by way of limitation with regard to the claimed invention. [0012] FIGS. 1 and 3 are functional block diagrams of illustrative embodiments of an emulation and trace storage system that produces compressed trace data in accordance with at least one aspect of the present invention. [0013] FIG. 2 is a functional block diagram of an illustrative embodiment of an emulator in accordance with at least one aspect of the present invention. [0014] FIG. 4 is a functional block diagram of the emulation system of FIGS. 1 and 2, showing additional detail within an emulation chip. [0015] FIG. 5 is a circuit diagram of an illustrative embodiment of a delta detector for receiving the output of a scan chain in accordance with at least one aspect of the present invention. [0016] FIG. 6 is a circuit diagram of a portion of an illustrative embodiment of a scan chain with an integrated delta detector in accordance with at least one aspect of the present invention. [0017] FIG. 7 is a graphical representation of an illustrative embodiment of trace data compaction and equalization in accordance with at least one aspect of the present invention. [0018] FIG. 8 is a functional block diagram of an illustrative embodiment of an event detector in accordance with at least one aspect of the present invention. [0019] FIGS. 9 and 10 are graphical representations of data that may be generated as a result of compression in accordance with at least one aspect of the present invention. Continue reading about Compression of emulation trace data... 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