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Components, methods and assemblies for multi-chip packagesRelated Patent Categories: Semiconductor Device Manufacturing: Process, Packaging (e.g., With Mounting, Encapsulating, Etc.) Or Treatment Of Packaged SemiconductorComponents, methods and assemblies for multi-chip packages description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070166876, Components, methods and assemblies for multi-chip packages. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS-REFERENCE TO RELATED APPLICATION [0001] This application is a divisional application of U.S. patent application Ser. No. 10/683,097 filed on Oct. 10, 2003, entitled "Components, Methods and Assemblies For Multi-Chip Packages", which claims the benefit of U.S. Provisional Patent Application Ser. No. 60/418,241, filed Oct. 11, 2002, the disclosures of which are hereby incorporated by reference herein. BACKGROUND OF THE INVENTION [0003] The present invention relates to microelectronic assemblies and to components and methods used for making the same. [0004] Microelectronic elements such as semiconductor chips ordinarily are mounted on circuit panels such as circuit boards. For example, a packaged semiconductor chip may have an array of bonding contacts on a bottom surface of the package. Such a package can be mounted to a corresponding array of bonding contacts exposed at a top surface of a circuit board by placing the package on the circuit board with the bottom surface of the package facing downwardly and confronting the top surface of the circuit board, so that each bonding contact on the package is aligned with a corresponding bonding contact on the circuit board. Masses of a conductive bonding material--mounting masses--typically in the form of solder balls, are provided between the bonding contacts of the package and the bonding contacts of the circuit board. In typical surface-mounting techniques, solder balls are placed on the bonding contacts of the package before the package is applied to the circuit board. [0005] Ordinarily, numerous microelectronic elements are mounted side-by-side on the circuit board and interconnected to one another by electrically conductive traces connecting the various bonding contacts. Using this conventional approach, however, the circuit board must have an area at least equal to the aggregate area of all of the microelectronic elements. Moreover, the circuit board must have all of the traces needed to make all of the interconnections between microelectronic elements. In some cases, the circuit board must include many layers of traces to accommodate the required interconnections. This materially increases the cost of the circuit board. Typically, each layer extends throughout the entire area of the circuit board. Stated another way, the number of layers in the entire circuit board is determined by the number of layers required in the area of the circuit board having the most complex, densely packed interconnections. For example, if a particular circuit requires six layers of traces in one small region but only requires four layers in the remainder of the circuit board, the entire circuit board must be fabricated as a six-layer structure. [0006] These difficulties can be alleviated to some degree by connecting related microelectronic elements to one another using an additional circuit panel so as to form a sub-circuit or module, also referred to herein as a "multi-chip module" or MCM. The multi-chip module, in turn, is mounted to the main circuit board. The main circuit board need not include the interconnections made by the circuit panel of the module. It is possible to make such a multi-chip module in a "stacked" configuration, so that some of the packaged chips or other microelectronic elements in the module are disposed on top of other chips or microelectronic elements in the same module. Thus, the multi-chip module as a whole can be mounted in an area of the main circuit board less than the aggregate area of the individual microelectronic elements in the module. However, the additional circuit panel and the additional layer of interconnections between this circuit panel and the main circuit board consume additional space. In particular, the additional circuit panel and additional layer of interconnections between the additional circuit panel and the main circuit panel add to the height of the multi-chip module, e.g., the distance by which the module projects above the top surface of the main circuit board. This is particularly significant where the module is provided in a stacked configuration and where low height is essential, as, for example, in assemblies intended for use in miniaturized cellular telephones and other devices to be worn or carried by the user. [0007] The additional space consumed by mounting packaged semiconductor chips on a separate module circuit panel can be saved by integrating the circuit panel of the module with a part of the package itself, commonly referred to as a package substrate. For example, several bare or unpackaged semiconductor chips can be connected to a common substrate during the chip packaging operation. Packages of this nature can also be made in a stacked arrangement. Such multi-chip packages can include some or all of the interconnections among the various chips in the package and can provide a very compact assembly. The main circuit board can be simpler than that which would be required to mount individual packaged chips in the same circuit. Unfortunately, these types of packages are difficult to repair, let alone test, after assembly. In addition, this approach requires unique packages for each combination of chips to be included in the package. For example, in the cellular telephone industry, it is a common practice to use the same field programmable gate array ("FPGA") or application specific integrated circuit ("ASIC") with different combinations of static random access memory ("SRAM") and flash memory so as to provide different features in different cellular telephones. This increases the costs associated with producing, handling and stocking the various packages. [0008] Thus, still further improvements in stacked chip assemblies would be desirable. SUMMARY OF THE INVENTION [0009] One aspect of the invention provides a separate circuit module, or multi-chip module (MCM), wherein packaged semiconductor chips are attached to both sides of an interposer using connections in accordance with a land grid array (LGA) connection. Most preferably, no underfill material is used in the joints between the packaged semiconductor chips and the interposer to provide low overall height for the MCM. It is another object of the invention to improve the test and repair capabilities of the multi-chip module. [0010] Another aspect of the invention provides for an ultra-thin system-in-a-package (SIP) structure. [0011] Another aspect of the invention provides a stacked electronic assembly comprising a plurality of multi-chip modules. Each multi-chip module further comprising packaged semiconductor chips attached to both sides of an interposer using LGA connections. No underfill material is used in the stacked electronic assembly. [0012] Another aspect of the invention relates to methods of making multi-chip assemblies of the types described herein. A substrate comprises electrically conductive terminals accessible at both surfaces of the substrate. Most preferably, the terminals are disposed in accordance with an LGA pattern. The steps of making the multi-chip module include providing a substrate in the form of a flat sheet as described herein, assembling a plurality of packaged semiconductor chips to both surfaces of the substrate such that no underfill is applied to either surface of the multi-chip module. [0013] Another aspect of the invention relates to methods of attaching a multi-chip module of the types described herein to a circuit board. In particular, a multi-chip module of the types described herein may be subject to warpage. The steps of making the circuit board include positioning a warped multi-chip module over a portion of a circuit board for attachment thereto; and reflowing the multi-chip module to remove the warpage. In particular, reflow is performed at a temperature that is within or above a temperature range window. The temperature range window relates to prior assembly of the multi-chip module and includes those temperatures used to cure solder masks, etc. By performing reflow at a temperature within or above the temperature window, the warped multi-chip module relaxes and becomes flatter for mounting to the circuit board. BRIEF DESCRIPTION OF THE DRAWINGS [0014] FIGS. 1 and 2 are illustrative diagrammatic views of packaged semiconductor chips; [0015] FIG. 3 is a diagrammatic view of a multi-chip module in accordance with the principles of the invention; [0016] FIGS. 4 and 5 are illustrative cross-sections of a multi-chip module in accordance with the principles of the invention; [0017] FIG. 6 is a diagrammatic top plan view of the multi-chip module of FIG. 3; [0018] FIG. 7 is a diagrammatic bottom plan view of the multi-chip module of FIG. 3; [0019] FIG. 8 is an illustrative flow chart for use in assembling a multi-chip module in accordance with the principles of the invention; [0020] FIG. 9 is a diagrammatic view illustrating possible warpage of a multi-chip module; [0021] FIG. 10 is an illustrative flow chart for use in mounting a multi-chip module in accordance with the principles of the invention; Continue reading about Components, methods and assemblies for multi-chip packages... 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