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Compliant electrical contactsRelated Patent Categories: Metal Working, Method Of Mechanical Manufacture, Electrical Device Making, Conductor Or Circuit Manufacturing, On Flat Or Curved Insulated Base, E.g., Printed Circuit, Etc.Compliant electrical contacts description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20080000080, Compliant electrical contacts. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This application is a divisional of U.S. application Ser. No. 10/906,111 filed Feb. 3, 2005, the complete disclosure of which, in its entirety, is herein incorporated by reference. BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The invention provides a method of forming compliant electrical contacts that includes patterning a conductive layer into an array of compliant members, and then joining the array of compliant members to contact pads on a wafer. [0004] 2. Description of the Related Art [0005] Electrical interconnections are often needed between integrated circuits, packages, boards, wafers, probes and other hardware which may be made from similar or dissimilar materials and may be coplanar or non-coplanar in nature. Often many connections are needed with semiconductor devices. Further, the features sizes and pitch of the connections to be interconnected are increased in number and reduced in size with advances of new generations of products over time. The characteristics that are desirable include the ability to have good electrical conduction while maintaining low electrical parasitics such as low inductance and capacitance for signal connections, provide good current carrying capability for power and ground connections, provide good mechanical integrity so electrical continuity can be assured even within or between different materials which may undergo expansion and contraction during power up, power down, thermal cycles, etc. This can produce stress and strains in the interconnection structures and thus lead to fatigue, opens, or electrical failures depending on the structure and application use conditions. [0006] Chip interconnect reliability and processing requirements are dramatically changing with the industry-wide change from leaded solders to lead-free solder metallurgy. Moving to a lead-free interconnect technology typically induces reliability concerns due to limited data for specific application reliability and in some cases poor thermal cycling performance of non-leaded systems and structure, resulting in device failures. In some cases, solutions have addressed the reliability concerns using various approaches, however the interconnect resistance has increased, which is also undesirable. Current connections to wafers do not give sufficient compliance to movement. [0007] The below-referenced U.S. patents disclose embodiments that were satisfactory for the purposes for which they were intended. The disclosures of the below-referenced prior U.S. patents, in their entireties, are hereby expressly incorporated by reference into the present invention for purposes including, but not limited to, indicating the background of the present invention and illustrating the state of the art. Further, the following U.S. patents explain many well known manufacturing processes/materials that can be used to form components mentioned below; however, the following U.S. patents do not disclose the unique methodology and/or structural features included within the invention, even if the inventive features utilize well known manufacturing processes/materials to achieve the unique methodology/structure. So as to not obscure the salient features of the invention, a detailed discussion of such well-known processing methods and materials is not included herein. [0008] U.S. Pat. No. 6,528,349 shows monolithically fabricated compliant wafer level features fabricated on the wafer as additional steps of processing a wafer. These steps build a compliant interconnection up from the wafer utilizing photolithography, deposition processes (such as plating or sputter coating) to sequentially build a compliant interconnection off of a die pad, and forming solder for connection to a corresponding package for interconnection. When the compliant members are formed on the wafer, the processing and materials that can be used are limited so as not to damage the wafer or its internal circuitry. [0009] Other references have shown the use of materials such as polymer materials to enhance the compliance of the interconnection (U.S. Pat. No. 6,690,081 and U.S. patent application 2003/0122229). Such references show compliant connections on a wafer at densities as high as 10000 to 20000 connections percentimeter squared. Again, however, while the monolithic fabrication of compliant members on a wafer can provide benefit by using semiconductor tools and sequential build up operations, this processing is limited to processes which do not damage the circuits and underlying interconnections. [0010] These restrictions that result from forming the compliant members on the wafer limit the desired compliance of the build up connections. This can also negatively impact yields of useful and often expensive chips especially if the interconnection build up has defects which causes fall out or may degrade the performance or reliability of underlying devices and interconnection due to the multitude of additional processing steps being utilized. Other U.S. patents that are incorporated herein by reference including U.S. Pat. Nos. 5,023,205; 6,187,615; 5,736,448; 6,281,111 illustrate additional well known processing relating to compliant connections. SUMMARY OF THE INVENTION [0011] The invention provides a method of forming a compliant electrical contact that includes patterning a conductive layer into an array of compliant members. The array of compliant members is then positioned to be in contact with electrical connection pads on an integrated circuit wafer and the compliant members are joined to the pads. Then, the supporting layer that supported the compliant members is removed to leave the compliant members connected to the pads. [0012] To join the compliant members to the pads, the invention can exert pressure between the supporting member and the wafer (to cause the compliant members to press against the pads) and then heat the compliant members and the wafer to join the two together. Alternatively, prior to positioning the array of compliant members next to the pads, the invention can position a metallic paste layer over the pads and then laser transfer the metallic paste onto the pads. Then, the metallic paste can be reflowed in order to join the compliant members to the pads. In another alternative, the invention can form solder on exposed ends of the compliant members prior to joining the compliant members with the pads. In another alternative, the invention can form the compliant interconnections on another silicon wafer and can shape the compliant interconnections by using etched shapes in the silicon or by fabricating the structures on the surface of the wafer where the resulting compliant interconnections can be transferred or permanently attached to a wafer with circuitry using copper to copper bonding, or alternate bonding technology. [0013] Because the invention forms the array of compliant members separately from the more expensive active circuit wafer and subsequently joins the array of compliant members to the active circuit wafer, the compliant members can be shaped and inspected/tested before positioning the array of compliant members in contact with the pads. Further, this process allows the alloy that is used for a compliant members to be made at temperatures that exceed those which would damage the wafer and associated active or passive circuitry. In addition, this aspect of the invention allows the compliant members to be plated, and where appropriate, heat treated using processing which would damage the integrated circuit wafer. Thus, by forming compliant members separately from the wafer (as opposed to forming the compliant members sequentially on the surface of the wafer) and then connecting the compliant members to the wafer, the invention is not restricted from structures, processing techniques, materials, etc. that would normally damage the wafer and its associated circuitry. [0014] The resulting structure has a number of advantages including that the compliant members comprise an alloy (in one example e.g., copper beryllium, W, Mo, Ni, Cu, Au, Pt, Pd, composites or alloys but is not limited to these and is capable of being formed only using processing that would damage the integrated circuit structure if built sequentially after fabrication of circuits on the wafer. Further, the compliant members can comprise plated materials and temperature annealed or heat treated structures and materials capable of being formed only using processing that would damage the integrated circuit structure. The invention also permits a non-alloy solder (e.g., copper) to join the compliant members to the contact pads. In addition, the process permits fabrication and interconnection of two or more stacked or adjacent surfaces by incorporation of one or more joining compliant interconnection layers. [0015] These, and other, aspects and objects of the present invention will be better appreciated and understood when considered in conjunction with the following description and the accompanying drawings. It should be understood, however, that the following description, while indicating preferred embodiments of the present invention and numerous specific details thereof, is given by way of illustration and not of limitation. Many changes and modifications may be made within the scope of the present invention without departing from the spirit thereof, and the invention includes all such modifications. BRIEF DESCRIPTION OF THE DRAWINGS [0016] The invention will be better understood from the following detailed description with reference to the drawings, in which: [0017] FIG. 1 is a schematic cross-sectional diagram of a mask formed over a compliant conductive material; [0018] FIG. 2 is a schematic cross-sectional diagram of patterned compliant conductive material; [0019] FIG. 3 is a schematic cross-sectional diagram of compliant members; [0020] FIG. 4 is a schematic cross-sectional diagram of compliant members being connected to a wafer; Continue reading about Compliant electrical contacts... Full patent description for Compliant electrical contacts Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Compliant electrical contacts patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. 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