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  Complementary metal-oxide-semiconductor (cmos) image sensor and fabricating method thereofUSPTO Application #: 20080093633Title: Complementary metal-oxide-semiconductor (cmos) image sensor and fabricating method thereof Abstract: A complementary metal-oxide-semiconductor (CMOS) image sensor including a substrate, a p type well, a light emitting diode, a p type gate structure and a plurality of n type gate structures is provided. The substrate has a photo sensitive region and a transistor device region, and the p type well is disposed in the substrate. The light emitting diode is disposed in the p type well and the substrate of the photo sensitive region. The p type gate structure is disposed on the substrate of the transistor device region. The n type gate structures are disposed on the substrate of the transistor device region. (end of abstract)
Agent: Jianq Chyun Intellectual Property Office - Taipei, om Inventor: Jhy-Jyi Sze USPTO Applicaton #: 20080093633 - Class: 257225 (USPTO) The Patent Description & Claims data below is from USPTO Patent Application 20080093633. Brief Patent Description - Full Patent Description - Patent Application Claims
BACKGROUND OF THE INVENTION [0001]1. Field of the Invention [0002]The present invention relates to an image sensor and a fabricating method thereof. More particularly, the present invention relates to a complementary metal oxide semiconductor (CMOS) image sensor and a fabricating method thereof. [0003]2. Description of Related Art [0004]The process of forming a complementary metal oxide semiconductor (CMOS) image sensor is compatible to the process of forming a complementary metal oxide semiconductor (CMOS) transistor. Consequently, CMOS image sensors and CMOS transistors can be fabricated with other peripheral circuits on the same chip. Thus, the power consumption and the fabricating cost of image sensors can be significantly reduced. In recent years, the CMOS image sensor has replaced the charge-coupled device (CCD) in the lower level application and has become popular day by day. [0005]The CMOS image sensor is composed of a light emitting diode and a plurality of transistors. The light emitting diode is formed of a p-n junction including an n type doped region and the p type substrate. The transistors are n type transistors having an n type gate (n-poly NMOS). Currently, the CMOS image sensor includes two configurations of 3-T and 4-T. The 3-T configuration means the CMOS image sensor includes a reset transistor (Rx), a source coupling transistor (Dx), a select transistor (Sx) and a light emitting diode, while the 4-T configuration means the CMOS image sensor has a transfer transistor (Tx), a reset transistor, a source coupling transistor, a select transistor and a light emitting diode. Recently, the CMOS image sensor usually has a disadvantage of current leakage. Generally, the light emitting diode and the transistors of the CMOS image sensor would generate current leakage. The problem of current leakage as above mentioned would cause large dark current in the CMOS image sensor, such that the read noise is increased and the image quality is deteriorated, and thus the device performance is decreased. [0006]In particular, for the 4-T CMOS image sensor, the dark current in the CMOS image sensor occurs due to the current leakage of the transfer transistor. Therefore, how to reduce the current leakage of the image sensor becomes an important development topic. SUMMARY OF THE INVENTION [0007]The objective of the present invention is to provide a CMOS image sensor and a fabricating method thereof capable of reducing the current leakage and avoiding the dark current so as to improve the image quality and device performance. [0008]The present invention provides a method of fabricating a CMOS image sensor. A substrate having a photo sensitive region and a transistor device region is provided. Next, a p type well is formed in the substrate of the transistor device region. A dielectric layer and an un-doped polysilicon layer are sequentially formed on the substrate. Thereafter, a first mask layer is formed to cover the un-doped polysilicon layer in the photo sensitive region and a portion of the transistor device region. A first ion implantation process is performed to implant an n type impurity into the exposed un-doped polysilicon layer so as to form an n type polysilicon layer, and then the first mask layer is removed. Next, a second mask layer is formed to cover the n type polysilicon layer. A second ion implantation process is performed to implant a p type impurity into the exposed un-doped polysilicon layer so as to form a p type polysilicon layer, and then the second mask layer is removed. Thereafter, the dielectric layer, the n type polysilicon layer and the p type polysilicon layer are patterned to form a plurality of n type gate structures and a p type gate structure on the p type well of the transistor device region. Then, a light emitting diode is formed in the substrate of the photo sensitive region. [0009]According to an embodiment of the present invention, the n type gate structures are the gate structures of three of a transfer transistor, a reset transistor, a source coupling transistor and a select transistor, and the p type gate structure is the gate structure of the other one of the transistors. [0010]According to an embodiment of the present invention, the n type gate structures are the gate structures of two of a reset transistor, a source coupling transistor and a select transistor, and the p type gate structure is the gate structure of the other one of the transistors. [0011]According to an embodiment of the present invention, the n type impurity is phosphorous (P) or arsenic (As). [0012]According to an embodiment of the present invention, the concentration of the n type impurity is between 1.times.10.sup.14 and 5.times.10.sup.15 ions/cm.sup.2. [0013]According to an embodiment of the present invention, the p type impurity is boron (B) or boron difluoride (BF.sub.2). [0014]According to an embodiment of the present invention, the concentration of the p type impurity is between 1.times.10.sup.13 and 5.times.10.sup.15 ions/cm.sup.2. [0015]According to an embodiment of the present invention, the light emitting diode is formed by doping process. [0016]The present invention also provides a method of fabricating a CMOS image sensor. A substrate having a photo sensitive region and a transistor device region is provided. Next, a p type well is formed in the substrate of the transistor device region. A dielectric layer and an un-doped polysilicon layer are sequentially formed on the substrate. Next, a first ion implantation process is performed to implant an n type impurity into the un-doped polysilicon layer so as to form an n type polysilicon layer. Thereafter, a mask layer is formed to expose the un-doped polysilicon layer of the photo sensitive region and a portion of the transistor device region. A second ion implantation process is performed to implant a p type impurity so as to make the exposed n type polysilicon layer transferring into a p type polysilicon layer. Thereafter, the dielectric layer, the n type polysilicon layer and the p type polysilicon layer are patterned to form a plurality of n type gate structures and a p type gate structure on the p type well of the transistor device region. Then, a light emitting diode is formed in the substrate of the photo sensitive region. [0017]According to an embodiment of the present invention, the n type gate structures are the gate structures of three of a transfer transistor, a reset transistor, a source coupling transistor and a select transistor, and the p type gate structure is the gate structure of the other one of the transistors. [0018]According to an embodiment of the present invention, the n type gate structures are the gate structures of two of a reset transistor, a source coupling transistor and a select transistor, and the p type gate structure is the gate structure of the other one of the transistors. [0019]According to an embodiment of the present invention, the n type impurity is phosphorous (P) or arsenic (As). [0020]According to an embodiment of the present invention, the concentration of the n type impurity is between 1.times.10.sup.14 and 5.times.10.sup.15 ions/cm.sup.2. [0021]According to an embodiment of the present invention, the p type impurity is boron (B) or boron difluoride (BF.sub.2). [0022]According to an embodiment of the present invention, the concentration of the p type impurity is between 1.times.10.sup.13 and 5.times.10.sup.15 ions/cm.sup.2. Continue reading... Full patent description for Complementary metal-oxide-semiconductor (cmos) image sensor and fabricating method thereof Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Complementary metal-oxide-semiconductor (cmos) image sensor and fabricating method thereof patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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