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  Compact linked-list-based multi-threaded instruction graduation bufferUSPTO Application #: 20070204139Title: Compact linked-list-based multi-threaded instruction graduation buffer Abstract: A processor and instruction graduation unit for a processor. In one embodiment, a processor or instruction graduation unit according to the present invention includes a linked-list-based multi-threaded graduation buffer and a graduation controller. The graduation buffer stores identification values generated by an instruction decode and dispatch unit of the processor as part of one or more linked-list data structures. Each linked-list data structure formed is associated with a particular program thread running on the processor. The number of linked-list data structures formed is variable and related to the number of program threads running on the processor. The graduation controller includes linked-list head identification registers and linked-list tail identification registers that facilitate reading and writing identifications values to linked-list data structures associated with particular program threads. The linked-list head identification registers determine which executed instruction result or results are next to be written to a register file. (end of abstract) Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c. - Washington, DC, US Inventor: Kjeld Svendsen USPTO Applicaton #: 20070204139 - Class: 712218000 (USPTO) Related Patent Categories: Electrical Computers And Digital Processing Systems: Processing Architectures And Instruction Processing (e.g., Processors), Dynamic Instruction Dependency Checking, Monitoring Or Conflict Resolution, Commitment Control Or Register Bypass The Patent Description & Claims data below is from USPTO Patent Application 20070204139. Brief Patent Description - Full Patent Description - Patent Application Claims
FIELD OF THE INVENTION [0001] The present invention relates generally to processors and more particularly to processors having an out-of-order execution pipeline. BACKGROUND OF THE INVENTION [0002] Reduced Instruction Set Computer (RISC) processors are well known. RISC processors have instructions that facilitate the use of a technique known as pipelining. Pipelining enables a processor to work on different steps of an instruction at the same time and thereby take advantage of parallelism that exists among the steps needed to execute an instruction. As a result, a processor can execute more instructions in a shorter period of time. Additionally, modern Complex Instruction Set Computer (CISC) processors often translate their instructions into micro-operations (i.e., instructions similar to those of a RISC processor) prior to execution to facilitate pipelining. [0003] Many pipelined processors, especially those used in the embedded market, are relatively simple single-threaded in-order machines. As a result, they are subject to control, structural, and data hazard stalls. More complex processors are typically multi-threaded processors that have out-of-order execution pipelines. These more complex processors schedule execution of instructions around hazards that would stall an in-order machine. [0004] A conventional multi-threaded out-of-order processor has multiple dedicated buffers that are used to reorder instructions executed out-of-order so that each instruction graduates (i.e., writes its result to a general purpose register file and/or other memory) in program order. For example, a conventional N-threaded out-of-order processor has N dedicated buffers for ensuring instructions graduate in program order; one buffer for each thread that can be run on the processor. A shortcoming of this approach, for example, is that it requires a significant amount of integrated circuit chip area to implement N separate buffers. This approach can also degrade performance in some designs when only a single program thread is running on a multi-threaded processor, for example, if each of the N buffers is limited in size in order to reduce the overall area of the N buffers. [0005] What is needed is a processor that overcomes the limitations noted above. BRIEF SUMMARY OF THE INVENTION [0006] The present invention provides a processor, an instruction graduation unit for a processor, and applications thereof. In one embodiment, a processor or an instruction graduation unit according to the present invention includes a linked-list-based multi-threaded graduation buffer and a graduation controller. [0007] The graduation buffer is used to temporarily store identification values generated by an instruction decode and dispatch unit of the processor. The identification values specify buffer registers used to temporarily store executed instruction results until the results are written to a register file. The identification values generated by the instruction decode and dispatch unit are stored in the graduation buffer and form part of one or more linked-list data structures. Each linked-list data structure formed is associated with a particular program thread running on the processor. Accordingly, the number of linked-list data structures formed is variable and related to the number of program threads running on the processor. [0008] The graduation controller is coupled to the graduation buffer and includes both linked-list head identification registers and linked-list tail identification registers. The linked-list head identification registers and the linked-list tail identification registers facilitate reading and writing identifications values generated by the instruction decode and dispatch unit of the processor to a linked-list data structure associated with a particular program thread. The linked-list head identification registers determine which executed instruction result or results are next to be written to the register file. [0009] Further embodiments, features, and advantages of the present invention, as well as the structure and operation of the various embodiments of the present invention, are described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS/FIGURES [0010] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate the present invention and, together with the description, further serve to explain the principles of the invention and to enable a person skilled in the pertinent art to make and use the invention. [0011] FIG. 1 is a diagram of a processor according to an embodiment of the present invention. [0012] FIG. 2 is a more detailed diagram of the processor of FIG. 1. [0013] FIG. 3 is a diagram of a first embodiment of a graduation buffer and a graduation controller according to the present invention. [0014] FIG. 4 is a simplified diagram of the graduation buffer and the graduation controller of FIG. 3. [0015] FIG. 5 is a first table illustrating operation of the graduation buffer and the graduation controller of FIG. 3. [0016] FIG. 6 is a second table illustrating operation of the graduation buffer and the graduation controller of FIG. 3. [0017] FIG. 7 is a diagram of a second embodiment of a graduation buffer and a graduation controller according to the present invention. [0018] FIG. 8 is a simplified diagram of the graduation buffer and the graduation controller of FIG. 7. [0019] FIG. 9 is a first table illustrating operation of the graduation buffer and the graduation controller of FIG. 7. [0020] FIG. 10 is a second table illustrating operation of the graduation buffer and the graduation controller of FIG. 7. Continue reading... Full patent description for Compact linked-list-based multi-threaded instruction graduation buffer Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Compact linked-list-based multi-threaded instruction graduation buffer patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Compact linked-list-based multi-threaded instruction graduation buffer or other areas of interest. ### Previous Patent Application: Device, system and method of tracking data validity Next Patent Application: Integrated circuit with memory and method of configuring a memory Industry Class: Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) ### FreshPatents.com Support Thank you for viewing the Compact linked-list-based multi-threaded instruction graduation buffer patent info. IP-related news and info Results in 0.57364 seconds Other interesting Feshpatents.com categories: Qualcomm , Schering-Plough , Schlumberger , Seagate , Siemens , Texas Instruments , |
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