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  Compact custom layout for rram column controllerUSPTO Application #: 20060085777Title: Compact custom layout for rram column controller Abstract: The present invention provides a layout method for a top module including instances of a base module in a memory matrix such as a RRAM memory matrix, and the like. The top module and the base module may each include data pins and at least one control pin, or the top module and the base module may each include data pins only and may not include any control pins. The data pins of the instances of the base module are replicated in the top module. When at least one control pin is included in the top module and the base module, a control signal may be shared among the instances of the base module and the top module by tying together corresponding control pins of the instances and a corresponding control pin of the top module. The present method may include steps as follows. At a library preparation stage, data pins (and control pins, if applicable) of standard cells in the top module are extended vertically for easy access. Then, positions for the data pins of the top module (and at least one control pin, if applicable) of the top module are assigned in the top module. The instances are arranged within the top module. Signal routing for the instances and the top module are implemented. Power routing is performed for the instances and the top module. (end of abstract) Agent: Lsi Logic Corporation - Milpitas, CA, US Inventors: Alexander E. Andreev, Ivan Pavisic, Anatoli Bolotov USPTO Applicaton #: 20060085777 - Class: 716008000 (USPTO) Related Patent Categories: Data Processing: Design And Analysis Of Circuit Or Semiconductor Mask, Circuit Design, Floorplanning The Patent Description & Claims data below is from USPTO Patent Application 20060085777. Brief Patent Description - Full Patent Description - Patent Application Claims
FIELD OF THE INVENTION [0001] The present invention generally relates to the field of integrated circuits, particularly to compact custom layout algorithms for a class of modules (e.g., RRAM column controllers) found in a memory matrix (e.g., a RRAM memory matrix). BACKGROUND OF THE INVENTION [0002] Platform-based IC (integrated circuit) design is a powerful concept for coping with the increased pressure on time-to-market, design and manufacturing costs encountered in the current IC market. A platform is a large-scale, high-complexity semiconductor device that includes one or more of the following elements: (1) memory; (2) a customizable array of transistors; (3) an IP (intellectual property) block; (4) a processor, e.g., an ESP (embedded standard product); (5) an embedded programmable logic block; and (6) interconnect. RapidChip.TM. developed by LSI Logic Corp. is an instance of a platform. The basic idea behind the platform-based design is to avoid designing and manufacturing a chip from scratch. Some portion of the chip's architecture is predefined for a specific type of application. Through extensive design reuse, the platform-based design may provide faster time-to-market and reduced design cost. [0003] Under a platform approach, there are two distinct steps entailed in creating a final end-user product: a prefabrication step and a customization step. In a prefabrication step, a slice is built on a wafer. A slice is a pre-manufactured chip in which all silicon layers have been built, leaving the metal layers or top metal layers to be completed with the customer's unique IP. For example, RapidSlice.TM. developed by LSI Logic Corp. is an instance of a slice. One or more slices may be built on a single wafer. It is understood that a slice may include one or more bottom metal layers or may include no metal layers at all. In a preferred embodiment of the prefabrication step, portions of the metal layers are pre-specified to implement the pre-defined blocks of the platform and the diffusion processes are carried out in a wafer fab. The base characteristics, in terms of the IP, the processors, the memory, the interconnect, the programmable logic and the customizable transistor array, are all pre-placed in the design and pre-diffused in the slice. However, a slice is still fully decoupled because the customer has not yet introduced the function into the slice. In a customization step, the customer-designed function is merged with the pre-defined blocks and the metal layers (or late-metal components) are laid down, which couple the elements that make up the slice built in the wafer fab, and the customizable transistor array is configured and given its characteristic function. In other embodiments, early-metal steps may be part of the pre-fabricated slice to reduce the time and cost of the customization step, resulting in a platform which is more coupled and specific. It is understood that a prefabrication step and a customization step may be performed in different foundries. For example, a slice may be manufactured in one foundry. Later, in a customization step, the slice may be pulled from inventory and metalized, which gives the slice its final product characteristics in a different foundry. [0004] A slice such as RapidSlice.TM. may contain several RRAMs (Reconfigurable RAMs, or Redundant RAMs, or RapidSlice.TM. RAMs). Each RRAM is a set of memories of the same type that are placed compactly. RRAMs include built-in testing and self-repairing components. Thus, it is desirable to provide compact custom layout algorithms for a class of modules (e.g., RRAM column controllers) found in a memory matrix (e.g., a RRAM memory matrix). SUMMARY OF THE INVENTION [0005] In an exemplary aspect, the present invention provides a layout method for a top module including instances of a base module in a memory matrix such as a RRAM memory matrix, and the like. For example, the top module may be a RRAM column controller. Throughout the present application, a top module is a concept relative to a base module and is a module including instances of a base module. It is understood that the terminology "top module" does not have a connotation of being physically on top of a base module and does not imply any physical relationship between a top module and a base module (or an instance of a base module). In one embodiment, the top module and the base module may each include data pins and at least one control pin. Alternatively, the top module and the base module may each include data pins only and may not include any control pins. The data pins of the instances of the base module are replicated in the top module. When at least one control pin is included in the top module and the base module, a control signal may be shared among the instances of the base module and the top module by tying together corresponding control pins of the instances and a corresponding control pin of the top module. The present method may include steps as follows. At a library preparation stage, data pins (and control pins, if applicable) of standard cells in the top module are extended vertically for easy access. Then, positions for the data pins of the top module (and at least one control pin, if applicable) of the top module are assigned in the top module. The instances are arranged within the top module. Signal routing for the instances and the top module are implemented. Power routing is performed for the instances and the top module. [0006] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed. The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate an embodiment of the invention and together with the general description, serve to explain the principles of the invention. BRIEF DESCRIPTION OF THE DRAWINGS [0007] The numerous advantages of the present invention may be better understood by those skilled in the art by reference to the accompanying figures in which: [0008] FIG. 1 is a schematic diagram of a top module including instances of a base module in accordance with an exemplary embodiment of the present invention; [0009] FIG. 2 is a flowchart of a layout method for a top module including instances of a base module in a memory matrix in accordance with an exemplary embodiment of the present invention; [0010] FIG. 3 is a schematic diagram illustrating a cell with four signal pins and standard power and ground pins after the signal pins are extended vertically for easy access in accordance with an exemplary embodiment of the present invention; [0011] FIG. 4 is a schematic diagram illustrating a top module after positions are assigned for signal pins of the top module and instances are arranged within the top module in accordance with an exemplary embodiment of the present invention; [0012] FIG. 5 is a schematic diagram illustrating a base module including a multiplexer MUX and a buffer BUF which buffers the output of MUX in accordance with an exemplary embodiment of the present invention; [0013] FIG. 6 is a schematic diagram illustrating a result after signal routing is implemented inside the top module shown in FIG. 4 which includes instances of the base module shown in FIG. 5 in accordance with an exemplary embodiment of the present invention; and [0014] FIG. 7 is a schematic diagram illustrating a result after power routing is performed for the top module and the instances of the base module shown in FIG. 6 in accordance with an exemplary embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION [0015] Reference will now be made in detail to the presently preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. [0016] The present invention provides layout algorithms (placement and routing) for a class of modules (e.g., RRAM column controllers) found in a memory matrix (e.g., a RRAM memory matrix). The present invention may be applied to similar modules found in memory test structures and elsewhere without departing from the scope and spirit of the present invention. [0017] The type of module M that this invention applies to is shown schematically in FIG. 1. A top module (Module M) includes multiple instances ins.sub.1, ins.sub.2, . . . , ins.sub.n, of the same module M.sub.0 (hereinafter "a base module"). Throughout the present application, a top module is a concept relative to a base module and is a module including instances of a base module. It is understood that the terminology "top module" does not have a connotation of being physically on top of a base module and does not imply any physical relationship between a top module and a base module (or an instance of a base module). In one embodiment, the top module and the base module may each include data pins and at least one control pin. Alternatively, the top module and the base module may each include data pins only and may not include any control pins. As an example, the following description of the present invention concerns with the top module and the base module each including data pins and at least one control pin. However, those of ordinary skill in the art will understand that the present invention may apply to the top module and the base module each including data pins only and no control pins without departing from the scope and spirit of the present invention. [0018] As shown in FIG. 1, there are two types of pins--data and control pins--on both the top module and the base module. Data pins from multiple instances of the base module are replicated in the top module, as shown in FIG. 1. Control signals, on the other hand, are shared among the instances of base module. Same control pins from different instances are tied together and connected to the corresponding pin on the top module (e.g., CT.sub.1 or CT.sub.2). [0019] The present invention provides algorithms and procedures for complete layout of the module M with a given overall width W. FIG. 2 is a flowchart of a layout method 200 for a top module including instances of a base module in a memory matrix in accordance with an exemplary embodiment of the present invention. The top module and the base module may each include data pins and at least one control pin. The data pins of the instances of the base module are replicated in the top module. A control signal is shared among the instances of the base module and the top module by tying together corresponding control pins of the instances and a corresponding control pin of the top module. Those of ordinary skill in the art will understand that the layout method 200 may apply to the top module and the base module each including data pins only and no control pins without departing from the scope and spirit of the present invention. Continue reading... Full patent description for Compact custom layout for rram column controller Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Compact custom layout for rram column controller patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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