Coded data generation or conversion inventions 05/06

20060109148 - Binary image-processing device and method using symbol dictionary rearrangement: Disclosed is binary image-processing device and method using symbol dictionary rearrangement. The binary image-processing device comprises a symbol-extracting unit for extracting symbols from an inputted binary image; a symbol-matching unit for matching a extracted symbol with a previously registered symbol and building a symbol dictionary; and a symbol dictionary rearrangement...

20060109146 - Digital circuit having a delay circuit for adjustment of clock signal timing: A digital circuit according to the present invention includes a pulse delay circuit where a driving current of an inverter is variable, for causing timing of a clock signal to be variable; and the pulse delay circuit has a stabilizing circuit for an amount of a pulse delay by a...

20060109149 - Digital signal coding apparatus, digital signal decoding apparatus, digital signal arithmetic coding method and digital signal arithmetic decoding method: In a bit stream syntax containing compressed video slice data for compressed video data of a slice structure, a slice header for compressed video slice data has attached thereto a slice start code, a register reset flag indicating whether a register value, which designates a status of a codeword occurring...

20060109147 - Frequency to digital conversion: A technique of processing an input signal having an input signal phase is disclosed. The technique includes determining a number of transitions of the input signal within a period having a start and an end. The technique includes determining a relative beginning phase of the input signal at the start...

20060109150 - Variable-length code decoding apparatus and method: There are provided a variable-length code decoding apparatus and method which can perform high-speed decoding processing without decreasing an image size and frame rate. A variable-length code decoding apparatus of this invention decodes a variable-length code containing a prefix and a suffix. This apparatus includes a prefix decoding unit which...

20060109151 - Circuit for zero offset auto-calibration and method thereof: A circuit for zero offset auto-calibration and a method thereof suitable for video signal analog-to-digital converters are provided. The circuit is connected between the last stage of a pipeline analog-to-digital converter (the pipeline ADC) and a differential signal buffer, comprised of an indicator signal generator, a calibration voltage generator and...

20060109152 - Error correction for rll channel bits in demodulation rules: RLL (Run Length Limited) code is a well-known channel coding technique, which has no error correction ability itself. The present invention discloses a decoding method, which corrects the channel bit errors via a modified demodulation table with added demodulation rules without increasing any modification circuit, to reduce channel bit errors...

20060109153 - Low power, high snr, high order delta sigma modulator stage having integrators with pipelined cross coupled input circuits: In a high order delta sigma modulator stage having integrators with pipelined cross coupled input circuits, the processing delay between an upstream integrator and a downstream integrator is decreased from a full cycle of a clock used to control the high order delta sigma modulator stage to a half cycle...

20060109154 - Multiplying digital to analog converter and multipath pipe line analog to digital converter using the same: A multiplying digital to analog converter comprising a digital to analog converter having a plurality of capacitors coupled in parallel, applying first signals to the capacitors during a sampling period, and applying second signals to the capacitors during an amplifying period, and an amplifier including a first amplifier electrically coupled...

20060109155 - Technique for improving modulation performance of translational loop rf transmitters: A transmit signal generated by the baseband processor in a translational loop type RF transmitter is “pre-distorted” so as to counter act magnitude distortion and group delay variation imposed by a narrow PLL signal filter. The pre-distortion occurs in two steps: a magnitude equalizer in the baseband processor pre-distorts the...

20060109156 - Trimming resistance ladders in analog-digital converters: A resistance ladder comprises a plurality of resistors in series, with taps for producing comparison voltage levels for an analog-to-digital converter (ADC), coupled at its ends to reference and common voltages via first and second adjustable resistances. The reference voltage is produced by an amplifier whose gain depends on a...

20060109157 - Apparatus and method for detecting voltage of an a/d converter: An apparatus and method are provided for detecting the voltage of an analog-to-digital converter. The apparatus comprises an analog-to-digital converter converting an analog signal into a digital signal, and a constant voltage device having one end connected to an input signal Vs to be detected, and a second end connected...

20060109158 - Addresses generation for interleavers in turbo encoders and decoders: An arrangement for generating addresses for interleaving/de-interleaving sequences (X1, X2, X3, . . . , XK) including a given number (K) of items, wherein each value for said given number (K) identifies a corresponding set of interleaving parameters (R, C, p, v). The arrangement has at least one memory unit...

20060103552 - Optical disk apparatus: In an optical disk apparatus, the polarity of synchronization information is adaptively set to thereby improve the quality of data recording and reproduction. When inserting and recording synchronization information, an encoder of an optical disk apparatus temporarily sets the polarity of the synchronization information to either a mark or a...

20060103553 - Keyboard arrangement and mobile communication device incorporating the same: The array of keys constituting a numeric phone keypad on a mobile communication device only partially overlaps the array of keys that make up the text input keypad creating an offset so that only subsets of the keys constituting the two keypads are common to both. With this configuration, the...

20060103554 - Fuse link trim algorithm for minimum residual: A parameter of an integrated circuit including a first trim array and a second trim array is trimmed by measuring an initial value of the parameter, determining whether the parameter exceeds a reference value, and as long as the parameter exceeds the reference value, repetitively blowing fuses associated with binarily...

20060103555 - Sample rate converter for reducing the sampling frequency of a signal by a fractional number: A sample rate converter reduces the sampling rate of a signal by a fractional number U/D, where U represents an up-sampling rate and D represents a down-sampling rate. The converter comprises an input for receiving an input data stream at a first rate and an FIR filtering stage. The FIR...

20060103556 - Lossless adaptive golomb/rice encoding and decoding of integer data using backward-adaptive rules: A method and system of lossless adaptive Golomb/Rice (G/R) encoding of integer data using a novel backward-adaptive technique having novel adaptation rules. The adaptive G/R encoder and decoder (codec) and method uses adaptation rules that adjust the G/R parameter after each codeword is generated. These adaptation rules include defining an...

20060103557 - Low-power serializer with half-rate clocking and method: A serializer for multiplexing 2N data streams, each data stream having a frequency of f/(2N), N being a positive integer. The serializer comprises 2N-1 instances of a dual-edge multiplexer flip-flop circuit, N frequency domains including a first frequency domain having the frequency f/2N and a last frequency domain having a...

20060103561 - Digital signal demodulator and wireless receiver using the same: A digital demodulator includes a resonator having a resonance frequency same as a carrier frequency to store a charge corresponding to a digital signal modulated by phase shift keying, a capacitor to store the charge of the resonator, an amplifier including an input node and an output node between which...

20060103559 - Method and apparatus of two stage scaling and quantization for coded communication systems: An apparatus comprising a first quantizer circuit, a memory and a second quantizer circuit. The first quantizer circuit may be configured to generate a first intermediate signal in response to (i) an input signal and (ii) a first scaling signal. The memory may be configured to (i) store the first...

20060103558 - Multiplexing: Embodiments of methods, apparatuses, systems and/or devices associated with multiplexing are disclosed....

20060103560 - Phase-compensated filter circuit with reduced power consumption: A filter circuit includes a plurality of integrator stages, each stage including a voltage-to-current converter to convert an input voltage into a current supplied to an output thereof and a capacitor coupled to the output of the voltage-to-current converter, a voltage charged in the capacitor being supplied to a next...

20060103564 - Balanced dual resistor string digital to analog converter system and method: A digital to analog converter system is disclosed for receiving an input signal and a sign bit signal that is indicative of the sign of the input signal. The digital to analog converter system includes first and second pairs of resistor strings, and first and second switching networks. A first...

20060103563 - Data driver, flat panel display and data converting method: A data driver in a flat panel display comprises: a latch for receiving a data signal in series, and for outputting the data signal in parallel; and a digital-to-analog (D/A) converter for converting the digital signal outputted by the latch into an analog signal. The D/A converter receives a reference...

20060103562 - Floating point idac: Circuits and methods to convert a digital floating-point number into an analog current have been achieved. The conversion is performed directly by using an exponential current digital-to-analog converter (DAC) and a cascaded linear current digital-to-analog converter (DAC). The exponential current DAC is converting exponentially the exponent of the floating-point number,...

20060103566 - Circuit for high-resolution phase detection in a digital rf processor: A novel time-to-digital converter (TDC) used as a phase/frequency detector and charge pump replacement in an all-digital PLL within a digital radio processor. The TDC core is based on a pseudo-differential digital architecture making it insensitive to NMOS and PMOS transistor mismatches. The time conversion resolution is equal to an...

20060103565 - Two-bit offset cancelling a/d converter with improved common mode rejection and threshold sensitivity: A two-bit offset canceling A/D converter with improved common mode rejection and threshold sensitivity for use in GPS receivers. A device in accordance with the present invention comprises a level shifter, the level shifter receiving a positive signal and a negative signal, the level shifter shifting the positive signal and...

20060097897 - Variable length decoding apparatus and method for the image format of a digital video camera: A variable length decoding apparatus and method for the image format of a digital video camera (DV) is provided for decoding the images of a digital video camera on the PASS2 decoding layer. The apparatus comprises a first register, a second register, a third register and a fourth register for...

20060097898 - Sampling circuit: A sampling circuit for compensating the phase difference of a sampling pulse due to a temperature variation to accurately sample input signals is provided. The sampling circuit samples received input signals. The sampling circuit includes a pulse generator for generating a pulse signal according to a timing at which an...

20060097899 - Adaptive-type sigma-delta a/d converter: A sigma-delta A/D converter includes an A/D converter configured to output a digital signal, a signal-magnitude detecting circuit coupled to the output of the A/D converter to output a control signal responsive to a magnitude indicated by the digital signal, a D/A converter coupled to the output of the A/D...

20060097900 - Photonic analog-to-digital converters using photonic crystals: A system and method for quantizing a photonic signal involves passing the photonic signal through a photonic crystal. The photonic crystal has localized defects for splitting the photonic signal into a plurality of quantized photonic components and for directing the quantized photonic components to a set of optical detectors. A...

20060097902 - Analog-to-digital conversion method, analog-to-digital converter, semiconductor device for detecting distribution of physical quantity, and electronic apparatus: In an analog-to-digital conversion method for converting a difference signal component representing a difference between a reference component and a signal component in an analog signal to be processed into digital data, in a first process, a signal corresponding to one of the reference component and the signal component is...

20060097901 - Analog-to-digital converter operable with staggered timing: An arrangement for a time interleaved analog-to-digital converter that converts an signal to a digital signal and has a converter array with a plurality of analog-to-digital converters arranged in a fixed sequence in parallel with one another and can be operated with staggered timing with respect to one another is...

20060097903 - Remote controller and method of operation of same: A remote controller, and a method of operation of the remote controller, the remote controller including a first key to select a predetermined functional mode, and a second key to select a sub mode of the functional mode, wherein an operational mode of the second key is changed to correspond...

20060092052 - Generating and searching compressed data: Data destined for a client is compressed at a server in a manner that produces a compressed data string that can be searched in its compressed state. The server constructs a code table that assigns codes from a standard code set (e.g., ASCII code set) that are normally unused to...

20060092047 - Low-cost absolute linear optical encoder: A Low-Cost Absolute Linear Optical Encoder (“LALOE”) for determining the absolute position of a read-head within the LALOE relative to a codestrip is disclosed. The LALOE may include an emitter module within the read-head, the emitter module having a plurality of light sources arranged in an light source pattern and...

20060092051 - Microcode configurable frequency clock: A microcode configurable frequency clock that may be used to control the speed of high speed comparison in an operational optical transceiver. The frequency clock includes a memory and a logic circuit. The memory receives microcode generated data relating to the desired speed of comparison. The logic circuit is configured...

20060092049 - Secure otp using external memory: A set-top-box has on-chip OTP memory emulated using an external flash memory and a series of on-chip fuses. The external memory is comprised of one or more regions, each having its own unique region identification. Each on-chip fuse corresponds to one of the memory regions and comprises a component which...

20060092048 - Semiconductor device: The present invention provides a semiconductor device with which it is possible to easily realize an information processing function according to an intended application while it is possible to suppress an increase in the management costs when, for example, making a change to the function, wherein a processing function setting...

20060092050 - Trellis constellation shaping: A method for trellis constellation shaping is disclosed. In one embodiment, this method comprises receiving two or more input bits and filtering at least one of the two or more input bits to create two or more filtered output bits. The step of filtering at least one input bit introduces...

20060092053 - Lossless adaptive encoding and decoding of integer data: A method and system of lossless compression of integer data using a novel backward-adaptive technique. The adaptive Run-Length and Golomb/Rice (RLGR) encoder and decoder (codec) and method switches between a Golomb/Rice (G/R) encoder mode only and using the G/R encoder combined with a Run-Length encoder. The backward-adaptive technique includes novel...

20060092054 - Recursive reduction of channel state feedback: Feedback bandwidth may be reduced in a closed loop MIMO system by Householder transformations and vector quantization using codebooks....

20060092055 - Generating and searching compressed data: Data destined for a client is compressed at a server in a manner that produces a compressed data string that can be searched in its compressed state. The server constructs a code table that assigns codes from a standard code set (e.g., ASCII code set) that are normally unused to...

20060092057 - Linearity corrector using filter products: A linearity corrector is provided that reduces distortion in a signal processing system, such as an ADC. The linearity corrector provides a first order signal path having distortion components connected to an adder, and a filter product circuit that is also connected to the adder. A method is provided for...

20060092056 - Sample rate doubling using alternating adcs: One embodiment of the invention includes a system comprising an analog baseband signal input, a conversion circuit with N Analog to Digital Converters (ADCs) operable to receive the analog baseband signal, and a Finite Impulse Response (FIR) filter operable to receive outputs of the N ADCs and to produce a...

20060092058 - Calibration system and method for a linearity corrector using filter products: A calibration system for calibrating a linearity corrector using the sum of filter products is proved, along with a method of calibrating the linearity corrector. The calibration system includes a first and second signal generator for introducing test signals into a signal processing system, such as an ADC. An acquisition...

20060092061 - Continuous-time delta-sigma adc with programmable input range: A scaled input current is produced that substantially matches the full scale input of a CTΔΣADC that substantially cancels an offset bias current component of the input current. A variable bias resistance value is coupled between the integrator input and one of a supply voltage and a circuit common. The...

20060092060 - Data modulating method and apparatus, data demodulating method and apparatus, and code arranging method: In a data demodulating method and apparatus, and a code arranging method, a multiplexer multiplexes an input data stream divided by a predetermined length into a plurality of types of pseudo random data streams using multiplexed information of predetermined bits by applying a predetermined multiplexing method to each of the...

20060092059 - Gain control in a signal path with sigma-delta analog-to-digital conversion: Automatic gain control is provided in a sigma-delta analog-to-digital converter. The automatic gain control is entirely or partly provided by an amplifier and an attenuator within the sigma-delta analog-to-digital converter. The amplifier within the sigma-delta time continuous loop prior to quantization and an attenuator in the feedback prior to summation...

20060092064 - Digital driver and display device: A digital driver for display devices which can prevent the delay of digital data and the extended transition time of the digital data, and thus can make good display, and a display device including the above-mentioned digital driver are disclosed. The digital driver according to the present invention is constituted...

20060092062 - Method and system for a glitch-free differential current steering switch circuit for high speed, high resolution digital-to-analog conversion: Provided are a method and system for reducing glitch in a switch circuit. A system includes a current-steering switch circuit including a main differential pair switch coupled to a first tail current having a first current value. Also included is an auxiliary differential pair switch connected to the main differential...

20060092063 - Pwm driver and class d amplifier using same: The objective of the invention is to provide a class D amplifier that can reduce aliasing noise. The class D amplifier has D/A converter 10 that operates at the first sampling frequency, and PWM driver 3 that receives the output from D/A converter 10. Said PWM driver 3 operates at...

20060092065 - Delay equalized z/2z ladder for digital to analog conversion: A Z/2Z ladder network includes an R/2R ladder network having capacitors coupled across series resistors within the R/2R ladder network, wherein the capacitors are sized to substantially match delays from nodes within the ladder network to an output node. The Z/2Z ladder network can be implemented within a digital to...

20060092066 - Delay equalized z/2z ladder for digital to analog conversion: A Z/2Z ladder network includes an R/2R ladder network having capacitors coupled across series resistors within the R/2R ladder network, wherein the capacitors are sized to substantially match delays from nodes within the ladder network to an output node. The Z/2Z ladder network can be implemented within a digital to...

20060092068 - Analog/digital conversion method and analog/digital conversion circuit: Paying attention to the difference between a subsequently inputted analog signal and a reference signal which is an analog signal converted to the digital signal immediately before for instance, changing timing dynamically for converting the analog signal to the digital signal, and converting an analog signal sampled at the timing...

20060092069 - Domino asynchronous successive approximation adc: The domino asynchronous successive approximation (ASA) analog-to-digital converter (ADC) converts an analog signal to an n-bits digital signal. The domino ASA ADC is made out of n-blocks, corresponding to the number of n-bits of the digital output. Each of these n-blocks generates a conversion bit and calibrates all following blocks,...

20060092067 - Front end circuit of voltage regulator: A front end circuit of a voltage regulator is provided. The front end circuit comprises an analog front end, a low-resolution analog-to-digital converter, and a reference voltage provider. The front end circuit emulates the performance of a high-resolution analog-to-digital converter by coupling the analog front end to the low-resolution analog-to-digital...

20060092070 - Method for correcting periodic sampling errors: In one representative embodiment, scaling factors and delay values associated with respective analog-to-digital converters (ADCs) of an interleaved ADC are stored in memory. As a digital sample from the interleaved ADC is received, a respective amplitude scaling factor is retrieved from memory and applied to the digital sample. Preferably, a...

20060092071 - Low-profile multi-turn encoder systems and methods: Various alternative embodiments of a multi-turn capacitive encoder device are disclosed. The device includes two members that are fixed relative to each other and that include respective capacitive electrodes that are capacitively coupled between the two members. The respective capacitive electrodes on one member act as transmitter electrodes and the...