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Cmos semiconductor devices having dual work function metal gate stacksCmos semiconductor devices having dual work function metal gate stacks description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070178634, Cmos semiconductor devices having dual work function metal gate stacks. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS-REFERENCE TO RELATED APPLICATION [0001]This application claims priority to Korean Patent Application No. 2006-0009367, filed on Jan. 31, 2006, which is incorporated herein by reference. TECHNICAL FIELD OF THE INVENTION [0002]The present invention relates, generally, to CMOS semiconductor devices having dual work function metal gate structures, as well as methods for fabricating dual metal gate stack structures providing separate gate work function control for PMOS and NMOS transistors. BACKGROUND [0003]In general, complementary metal oxide silicon (CMOS) semiconductor integrated circuits are formed with pairs of p-channel MOS (PMOS) and n-channel MOS (NMOS) transistors that work cooperatively with each other. CMOS semiconductor devices have higher operation efficiency and speed as compared to semiconductor devices formed using only PMOS transistors. Moreover, CMOS technology has good scaling characteristics, which has allowed development of semiconductor integrated circuit devices with increasingly higher integration densities. For these and other reasons, CMOS technology is commonly used to fabricate semiconductor devices for highly-integrated and high-performance applications. As CMOS technology downscales to nanometer levels and beyond, however, supply voltages and MOS transistor threshold voltages must also be continually scaled down to maintain high-performance and high-reliability. The aggressive downscaling of CMOS transistors has posed technological challenges with respect to development of gate stack structures having well-controlled and reproducible work functions/threshold voltages. [0004]Conventional CMOS fabrication techniques have employed a polycrystalline silicon (poly-Si) gate electrode process technology. FIG. 1A illustrates a conventional CMOS gate structure for MOS devices. FIG. 1A illustrates, a gate structure (10) formed on a semiconductor substrate (11). The gate structure (10) comprises a polysilicon (poly-si) gate electrode (10a) and a gate dielectric layer (10b) interposed between the gate electrode (10a) and the semiconductor substrate (11). In conventional gate stack designs, the gate dielectric layer (10b) is formed of a thermally grown silicon oxide, for example. The conventional gate structure (10) is insufficient to meet performance requirements in nanoscale CMOS technology. For example, at nanoscale design rules, the contact area of the poly-si gate electrode (10a) is significantly decreased, thereby requiring the thickness of the gate dielectric layer (10b), such as silicon oxide, to be decreased so as to maintain the gate capacitance that is required for proper device performance. [0005]When a poly-si gate stack structure (such as depicted in FIG. 1A) is formed with ultra-thin gate dielectric layer, device performance can be significantly degraded due to poly-si gate depletion (i.e., PDE (poly-gate depletion) effect), high gate resistance (smaller poly gate), increased gate dielectric tunneling leakage current, and other well-known problems. In particular, with poly-si gate depletion, a thin depletion layer is formed between the polysilicon gate electrode (10a) and the thin gate dielectric layer (10b), which increases the equivalent gate oxide thickness, resulting in a reduction of the total gate capacitance. [0006]To overcome problems associated with ultra-thin gate dielectric layers with poly-si gate stacks, high-K gate dielectric materials were considered for use as gate dielectric layers for poly-si gate stacks, which allowed for thicker gate dielectric layers under the same effective oxide thickness. This approach is effective to eliminate gate dielectric tunneling leakage, but there are compatibility problems when interfacing high-K dielectric materials with poly-Si gate electrodes. For examples in the absence of a diffusion barrier, oxidants in the high-k dielectric layer can easily diffuse into the poly-Si gate electrode forming a silicon oxide layer at the interface, resulting in decreased gate capacitance. Moreover, gate stack structures formed with high-k dielectrics layers interfaced with poly-Si gate electrodes do not overcome the PDE effect. [0007]Advanced gate stack solutions for nanoscale CMOS devices have employed high-K gate dielectric layers and metal gate electrodes to eliminate the problems of gate depletion, gate dielectric tunneling leakage and limitations in capacitance equivalent thickness downscaling. FIG. 1B illustrates a conventional CMOS gate structure (20) formed on a semiconductor substrate (21). The gate structure (20) comprises a polysilicon gate electrode (20a), a gate dielectric layer (20b), and a metal gate layer (20c) interposed between the poly-si electrode (20a) and the gate dielectric layer (20b). In some conventional designs, the same metallic material is used to form the metal gate layer (20c) for both the PMOS and NMOS gate stacks. Although the metal gate layer (20c) is effective to prevent gate depletion effects and dopant penetration from the poly-si gate into the gate dielectric layer, a drawback to this approach is that the threshold voltages of the PMOS and NMOS transistors are determined primarily by the work function of the inserted metal gate layer (20c). [0008]Ideally, metal gates with work functions corresponding to the conduction and valence band edges of Si are optimal for bulk-Si NMOS and PMOS transistors, respectively. However, single work function metal gate technologies must balance between the optimal work functions for the NMOS and PMOS transistors. For example, the metal gate layer for the NMOS and PMOS transistors may be formed of a metal having a Fermi level between energy levels of conduction and valence bands of the semiconductor layer. A drawback to this approach is that the threshold voltages Vth of the transistors are increased to levels that cannot be effectively reduced using channel counter doping techniques. Thus, single work function metal gate CMOS technologies may be ineffective to meet the threshold voltage scaling requirements that are needed to achieve low-power consumption and high speed device performance. [0009]Accordingly, dual work function metal gate CMOS technologies have been proposed in which the gate metal layers of the NMOS and PMOS gate stacks are formed from different metals having Fermi levels or work functions that correspond to the conduction and valance band edges of Si. For example, the metal layer in the NMOS gate stack can be formed of a metal having a Fermi level similar to the energy level of the conduction band of an n+-doped silicon layer, and the metal layer in the PMOS gate stack can be formed of a metal having a Fermi level similar to the energy level of the valence band of a p+-doped silicon layer. [0010]The development of dual work function metal gate techniques have posed technological challenges with regard to selection of metals having material properties which allow for separate control of the NMOS and PMOS gate work functions and which are suitable for integration with CMOS process technologies. By way of specific example, with dual metal gate fabrication processes, consideration should be given to the material characteristics of the gate metal/dielectric materials that are used to form the gate stacks so as to enable tight control and reproducibility of gate work functions. Moreover, consideration should be given the type of thin film processing techniques that are employed for device fabrication so as to prevent damage to the gate dielectric layer, which would degrade electrical performance or otherwise reduce the reliability and expected lifetime of the gate stack structure. [0011]For example, a conventional dual metal gate stack fabrication process includes forming a gate dielectric layer on a semiconductor substrate and forming a first metal layer on the gate dielectric layer, wherein the first metal layer is selected to set the work function for, e.g., the NMOS gate. Thereafter, the first metal layer is patterned to remove the portion of the first metal layer in the PMOS region. A second metal layer is then formed over the exposed gate dielectric layer in the PMOS region, wherein the second metal layer is selected to set the work function for, e.g., the PMOS gate. The second metal layer is then etched to remove the portion of the second metal layer in the NMOS region that is formed over the first metal layers. In this process, when the first metal layer is etched, the gate dielectric layer in the PMOS active region is used as an etch stop. Consequently, the gate dielectric layer in the PMOS stack can be damaged by the processing steps. [0012]In another conventional method, after the first metal layer is patterned (metal etch process), the gate dielectric layer is removed and a new gate dielectric layer is formed (i.e., removing potentially damaged gate dielectric layer). This approach is effective to improve the quality of the gate dielectric layer, but can result in damage to the first metal layer during fabrication of the new gate dielectric layer. For instance, the first metal layer can be oxidized when an oxidation process is employed to thermally grow an oxide layer for the gate dielectric. Moreover, when the new dielectric layer is formed using thin film deposition techniques (e.g., PVD), the exposed region of the active silicon and gate dielectric layer can be damaged during the plasma process. SUMMARY OF THE INVENTION [0013]In general, exemplary embodiments of the present invention include CMOS semiconductor devices having dual work function metal gate structures, as well as methods for fabricating dual metal gate stack structures providing dual gate work function control for PMOS and NMOS transistors. Exemplary fabrication techniques according to the invention in consideration of material characteristics and thin film processing techniques to significantly reduce or otherwise eliminate impact on gate dielectric reliability, [0014]In one exemplary embodiment of the invention a semiconductor device includes a semiconductor substrate having a dual-gate CMOS device formed on a front-side of the semiconductor substrate. The dual-gate CMOS device includes a PMOS device and an NMOS device. The PMOS device has a first gate stack formed of a gate insulator layer formed on the semiconductor substrate, a first conductive layer formed on the gate insulator layer, a second conductive layer formed on the first conductive layer, and a third conductive layer formed on the second conductive layer. The NMOS device has a second gate stack including a gate insulator layer formed on the semiconductor substrate, a first conductive layer formed on the gate insulator layer, and a second conductive layer formed on the first conductive layer. [0015]In one exemplary embodiment, the second conductive layers of the first and second gate stacks are formed from different conductive materials. In another embodiment, the first conductive layers of the first and second gate stacks are formed of a same conductive material having substantially the same thickness. For example, the first conductive layers of the first and second gate stack are formed of TaN or TiN. The thickness and the conductive material of the first conductive layers of the first and second gate stacks is selected to modulate a work function of the NMOS device. The thickness and a conductive material of the second conductive layer of the first gate stack is selected to modulate a work function of the PMOS device. [0016]In one exemplary embodiment, the first, second and third conductive layers of the first gate stack are formed of different conductive materials. The first conductive layer is preferably formed of a material that has an etch selectivity that is larger than an etch selectivity of the different materials that form the second and third conductive layers of the first gate stack with regard to an HF etching solution, for example. This enables removal of the portions of the second and third layers in the region of the second gate stack during a fabrication process. For example, the first, second and third conductive layers of the first gate stack of the PMOS device are formed of TaN, AlN and HfN, respectively. [0017]In other exemplary embodiments, the gate insulating layers of the first and second gate stacks is formed of a dielectric material having a dielectric constant in a range of about 8 and greater. An interfacial layer may be interposed between the gate insulating layers and the semiconductor substrate to prevent reaction between the high-k dielectric material and the silicon substrate. The gate insulating layers of the first and second gate stacks may be formed of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, yttrium oxide, or aluminum oxide. [0018]These and other exemplary embodiments, aspects, objects, features and advantages of the present invention will become apparent from the following detailed description of exemplary embodiments, which is to be read in connection with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS [0019]FIG. 1A is a cross-sectional schematic view of a conventional gate stack structure of a MOSFET transistor. Continue reading about Cmos semiconductor devices having dual work function metal gate stacks... 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