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Cmos image sensor using shared transistors between pixels having mirror symmetryRelated Patent Categories: Radiant Energy, Photocells; Circuits And Apparatus, Photocell Controlled Circuit, Plural Photosensitive Image Detecting Element ArraysCmos image sensor using shared transistors between pixels having mirror symmetry description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20060208163, Cmos image sensor using shared transistors between pixels having mirror symmetry. Brief Patent Description - Full Patent Description - Patent Application Claims
RELATED APPLICATIONS [0001] This is a continuation-in-part of U.S. patent application Ser. No. 10/771,839 filed Feb. 4, 2004 to which priority is claimed. TECHNICAL FIELD [0002] The present invention relates to CMOS image sensors, and more particularly, to a CMOS image sensor having a pixel architecture that allows for sharing of transistors within a vertical column between pixels and having mirror symmetry. BACKGROUND [0003] Integrated circuit technology has revolutionized various fields, including computers, control systems, telecommunications, and imaging. In the field of imaging, complimentary metal oxide semiconductor (CMOS) active pixel image sensors have made considerable inroads into applications served by charge coupled imaging devices. As noted in U.S. Pat. No. 5,625,210 to Lee et al. ("the '210 patent"), an active pixel sensor refers to an electronic image sensor with active devices, such as transistors, that are associated with each pixel. The active pixel sensor has the advantage of being able to incorporate both signal processing and sensing circuitry within the same integrated circuit because of the CMOS manufacturing techniques. [0004] A popular active pixel structure consists of four transistors and a pinned photodiode. The pinned photodiode has gained favor for its ability to have good color response for blue light, as well as advantages in dark current density and image lag. Reduction in dark current is accomplished by "pinning" the diode surface potential to the Pwell or Psubstrate (GND) through a P+ region. Because of the particular characteristics of pinned photodiodes, it is necessary to incorporate a transfer transistor that is not required in the three-transistor design discussed above. [0005] Still, one disadvantage of this design is that it requires four transistors for each pixel. Thus, a one-megapixel image sensor would require 4 million transistors simply for the imaging array. As higher resolution image sensors become popular, coupled with the need for higher integration densities, it is desirable to implement the "4-transistor" photodiode pixel while reducing the number of required transistors. BRIEF DESCRIPTION OF THE DRAWINGS [0006] The foregoing aspects and many of the attendant advantages of the invention will become more readily appreciated as the same become better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein: [0007] FIG. 1 is a schematic diagram of a prior art active pixel. [0008] FIG. 2 is a cross section view of the prior art active pixel of FIG. 1. [0009] FIG. 3 is a schematic diagram of a portion of a column of a prior art image sensor array. [0010] FIG. 4 is a schematic diagram of a portion of a column of an imaging array formed in accordance with the present invention. [0011] FIG. 5 shows an alternative embodiment of the present invention where 4 pixels share an amplifier and reset transistor and there is mirror symmetry. [0012] FIG. 6 shows a top layout view of the embodiment of FIG. 5 where 4 pixels share an amplifier and reset transistor and there is mirror symmetry. [0013] FIG. 7 shows a top layout view of the embodiment of FIG. 5 where 4 pixels share an amplifier transistor and reset transistor and there is mirror symmetry, wherein signal lines are schematically overlayed. [0014] FIGS. 8-10 show alternative layouts of the pixels in accordance with the present invention. [0015] FIG. 11 is a block diagram of a CMOS image sensor formed in accordance with the present invention. DETAILED DESCRIPTION [0016] The present invention relates to an active pixel design using a photodiode that requires fewer than an average of four transistors per active pixel. In the following description, numerous specific details are provided to provide a thorough understanding of the embodiments of the invention. One skilled in the relevant art will recognize, however, that the invention can be practiced without one or more of the specific details, or with other methods, components, etc. In other instances, well-known structures or operations are not shown or described in detail to avoid obscuring aspects of various embodiments of the invention. [0017] Reference throughout the specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout the specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. [0018] FIGS. 1 and 2 show a prior art active pixel 101 with a pinned photodiode 103, though it can be appreciated that the present invention may be used with other types of light sensitive elements, such as photodiodes, photogates, and partially pinned photodiodes. The pinned photodiode 103 is typically an N-well formed in a P-type substrate. A P+ region is formed atop of the N-well. A transfer gate (also referred to as a transfer transistor) controls the transfer of the signal from the pinned photodiode 103 to an output node 107 (also referred to as a floating node or FD). The output node 107 is connected to the gate of a source-follower transistor 109 (also referred to as a drive, amplifier, or output transistor). This results in the signal on the output node 107 being amplified and placed onto a column line out 111 (also referred to as a column readout line). [0019] A row select transistor (SEL) is used to select the particular pixel to be read out on the column line out 111. The row select transistor is controlled by a row select line. Further, a reset transistor 113 is used to reset the voltage on the sensing node. In order to reduce the leakage current from the silicon surface and kTC noise, the photodiode is typically provided with a pinning P+ surface shield layer at the silicon surface and is completely depleted. Continue reading about Cmos image sensor using shared transistors between pixels having mirror symmetry... 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