| Clock recovery circuit -> Monitor Keywords |
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  Clock recovery circuitRelated Patent Categories: Pulse Or Digital Communications, Synchronizers, Phase Displacement, Slip Or Jitter Correction, Phase Locking, With Charge Pump Or Up And Down CountersThe Patent Description & Claims data below is from USPTO Patent Application 20070041483. Brief Patent Description - Full Patent Description - Patent Application Claims
BACKGROUND OF THE INVENTION [0001] The present invention relates to a clock recovery circuit or a clock recovery unit suitable for high-speed differential interface. [0002] IEEE 1394.b standard defines small-amplitude differential serial data transfer. A clock recovery technique for recovering, from a data signal, a clock that is synchronized with the data signal is required for a receiving unit used in such serial data transfer. [0003] An example of a conventional clock recovery technique is shown in D. H. Wolaver, "Phase-Locked Loop Circuit Design", Section 10-2, pp. 213-216, Prentice Hall (1991). In this example, the format of a data signal is converted from NRZ (non-return-to-zero) to RZ (return-to-zero), and then a clock is recovered from the RZ data signal with a PLL (phase-locked loop). [0004] Basically, an H level duration and an L level duration of an NRZ data signal are both an integer multiple of one data interval. However, the H level duration, for example, may become shorter than one data interval due to a skew occurring in a differential amplifier or a differential transfer path, or due to process variations. In such a case, with the conventional example, a timing jitter occurs in the recovered clock. [0005] Moreover, with the conventional example, a phase detector and a charge pump of the PLL need to update the respective outputs for each data interval, whereby the operating speed of these elements limits the data rate. SUMMARY OF THE INVENTION [0006] A first object of the present invention is to suppress a timing jitter of a clock recovery circuit. [0007] A second object of the present invention is to provide a clock recovery unit suitable for high-speed data transfer. [0008] In order to realize the first object, the present invention provides a period in which a data transition characteristic of a driver or a receiver is adjusted so that a duty factor (DF) of a data signal is equal to 50% using a regular bit pattern, such as a clock, for example, which includes 1's and 0's alternating with each other, so that the clock can be recovered from the data signal, which is based on the adjusted transition characteristic, during an actual data transfer period. [0009] Specifically, a clock recovery circuit of the present invention includes: transceiver means for supplying a data signal, which is based on serial data having a regular bit pattern during a first period, and is based on serial data having an arbitrary bit pattern during a second period following the first period; a duty factor controller for adjusting a data transition characteristic of the transceiver means so as to reduce a duty factor error in a data signal supplied from the transceiver means in the first period, and having the adjusted data transition characteristic stored; and a clock recovery unit for recovering, from the data signal supplied from the transceiver means, a clock synchronized with the data signal in the second period. [0010] In order to realize the second object, the present invention provides a section for performing a phase detection and a charge pump operation in response to the rising edge of a data signal and another section for performing a phase detection and a charge pump operation in response to the falling edge of the data signal, and operates these sections in an interleaved manner. [0011] Specifically, a clock recovery unit of the present invention includes: a voltage controlled oscillator for generating a clock having a frequency according to a control voltage; a first charge pump and a second charge pump whose respective outputs are coupled to a common node; a first phase detector for detecting a phase error in the clock with respect to one of a rising edge and a falling edge of the data signal so as to control the first charge pump according to the phase error; and a second phase detector for detecting a phase error in the clock with respect to the other edge of the data signal so as to control the second charge pump according to the phase error, wherein a voltage that is generated at the common node by the first and second charge pumps is given to the voltage controlled oscillator as the control voltage so that the phase error detected by the first phase detector and the phase error detected by the second phase detector are both reduced. BRIEF DESCRIPTION OF THE DRAWINGS [0012] FIG. 1 is a block diagram illustrating a configuration of a clock recovery circuit according to a first embodiment of the present invention. [0013] FIG. 2 is a circuit diagram illustrating a specific configuration of a duty factor controller (DFC) in FIG. 1. [0014] FIG. 3 is a circuit diagram illustrating another specific configuration of the duty factor controller (DFC) in FIG. 1. [0015] FIG. 4 is a timing chart diagram illustrating an operation of the DFC of FIG. 3 in a case where a DF of a data signal in an adjustment period is less than 50%. [0016] FIG. 5 is a timing chart diagram illustrating an operation of the DFC of FIG. 3 in a case where a DF of a data signal in an adjustment period is greater than 50%. [0017] FIG. 6 is a block diagram illustrating a configuration of a clock recovery circuit according to a second embodiment of the present invention. [0018] FIG. 7 is a block diagram illustrating a configuration of a clock recovery circuit according to a third embodiment of the present invention. [0019] FIG. 8 is a timing chart diagram illustrating a PLL operation of a clock recovery unit (CRU) in FIG. 7. [0020] FIG. 9 is a timing chart diagram illustrating a DF adjustment operation of the CRU in FIG. 7. [0021] FIG. 10 is a block diagram illustrating a configuration of a clock recovery circuit according to a fourth embodiment of the present invention. Continue reading... Full patent description for Clock recovery circuit Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Clock recovery circuit patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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