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  Circuits for locally generating non-integral divided clocks with centralized state machinesUSPTO Application #: 20080030246Title: Circuits for locally generating non-integral divided clocks with centralized state machines Abstract: Circuitry for locally generating a ratio clock on a chip. The circuitry includes circuitry for generating a global clock signal having a global clock cycle. A state machine includes a counter going through a complete cycle in response to a non-integer number of global clock cycles, the state machine generating a control signal in response to the counter. Staging latches receive the control signal and generate a clock high signal and a clock low signal. A local pass gate receives the clock low signal and the clock high signal and generating an (n+0.5)-to-1 clock signal in response to at least one of the global clock signal, the clock high signal and the clock low signal. (end of abstract)
Agent: Cantor Colburn LLP-ibm Poughkeepsie - Bloomfield, CT, US Inventors: William V. Huott, Charlie C. Hwang, Timothy G. McNamara USPTO Applicaton #: 20080030246 - Class: 327151000 (USPTO) The Patent Description & Claims data below is from USPTO Patent Application 20080030246. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS REFERENCE TO RELATED APPLICATIONS [0001] This application is a continuation of U.S. application Ser. No. 11/341,032, filed Jan. 27, 2006, the contents of which are incorporated herein in their entirety. BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] This invention relates to generating a ratio clock signal using a global clock signal. More particularly, this invention relates to generating a ratio clock signal at any integer divided by two of a global clock signal. [0004] 2. Description of Background [0005] This application is related to U.S. patent application, filed on Jan. 27, 2006, entitled "Method for Locally Generating Non-Integral Divided Clocks with Centralized State Machines," Ser. No. 11/341,038, attorney docket number POU920050175US1 (Z04-0001), having William V. Huott, Charlie C. Hwang and Timothy G. McNamara and as named inventors, the entire contents of which are incorporated herein by reference. [0006] It is common for an integrated circuit chip (chip) to operate with multiple different clock speeds. Often, chip architecture allows different regions of the chip to have different clock speeds. To achieve multiple different clock speeds, a chip may employ multiple clock grids throughout the entire chip with each clock grid producing a distinct clock speed. However, employing multiple clock grids creates additional expense for chip production. Higher clock skews between clocks of different clock grids may reduce the maximum clock speed and reduce chip performance. Thus, to keep costs down and keep chip performance up, it has been common practice to use a single clock grid to generate a global clock and obtain different clock speeds by developing ratio clock speeds at a specific ratio to the global clock. [0007] It is common to use external control signals to develop derivative clock speeds at a ratio to the global clock. Additionally, absent external control signals, derivative clock speeds are generally limited to having whole number ratios to the global clock of, for example, 2-to-1, 4-to-1, etc. Generally, there is known in the art circuits which centrally generate clocks with multiple frequencies or phases with multiple phase locked loops, and which use an integral divider. Additionally, complex circuits used to generate derivative clock speeds may create a time delay between the global clock and the derivative clock. [0008] An existing solution is provided in U.S. patent application Ser. No. 11/056,024, the entire contents of which are incorporated herein by reference. This application describes a circuit and power device for a local state machine, which while well suited for its intended purpose, is primarily effective when there are only a few local circuits. However, there are embodiments where a high number of circuits use a non-integral divided clock locally. Thus, there is a need for a more compact solution than that described in U.S. patent application Ser. No. 11/056,024. SUMMARY OF THE INVENTION [0009] Embodiments include circuitry for locally generating a ratio clock on a chip. The circuitry includes circuitry for generating a global clock signal having a global clock cycle. A state machine includes a counter going through a complete cycle in response to a non-integer number of global clock cycles, the state machine generating a control signal in response to the counter. Staging latches receive the control signal and generate a clock high signal and a clock low signal. A local pass gate receives the clock low signal and the clock high signal and generating an (n+0.5)-to-1 clock signal in response to at least one of the global clock signal, the clock high signal and the clock low signal. [0010] Additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention. For a better understanding of the invention with advantages and features, refer to the description and to the drawings. TECHNICAL EFFECTS [0011] As a result of the summarized invention, technically we have achieved a solution that provides for generation of an (n+0.5)-to-1 ratio clock signal by providing a control signal to staging latches and combination logic. This allows the duty cycle of the ratio clock to be controlled by the control signal. BRIEF DESCRIPTION OF THE DRAWINGS [0012] The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other objects, features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which: [0013] FIG. 1 illustrates one example of multiple state machines in the central control unit for control signal generation; [0014] FIG. 2 illustrates a connection between a centralized state machine and local staging latches and logic; [0015] FIG. 3 illustrates one example of staging latches and logic for (n+0.5)-to-1 clock generation; [0016] FIG. 4 illustrates one example of a local passgate circuit; [0017] FIG. 5 illustrates one example of timing diagrams of two 1.5-to-1 clocks with different duty cycles; [0018] FIG. 6 illustrates one example of a method of determining required clkl and clkh pattern; [0019] FIG. 7 illustrates one example of determining the timing relationship of clkl and clkh; Continue reading... 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