| Circuit substrates, semiconductor devices, semiconductor manufacturing apparatuses, methods for manufacturing circuit substrates, and methods for manufacturing semiconductor devices -> Monitor Keywords |
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Circuit substrates, semiconductor devices, semiconductor manufacturing apparatuses, methods for manufacturing circuit substrates, and methods for manufacturing semiconductor devicesRelated Patent Categories: Metal Working, Method Of Mechanical Manufacture, Electrical Device Making, Conductor Or Circuit Manufacturing, On Flat Or Curved Insulated Base, E.g., Printed Circuit, Etc., Assembling To Base An Electrical Component, E.g., Capacitor, Etc.Circuit substrates, semiconductor devices, semiconductor manufacturing apparatuses, methods for manufacturing circuit substrates, and methods for manufacturing semiconductor devices description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070124928, Circuit substrates, semiconductor devices, semiconductor manufacturing apparatuses, methods for manufacturing circuit substrates, and methods for manufacturing semiconductor devices. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This application is a divisional of U.S. patent application Ser. No. 10/785,709 filed on Feb. 24, 2004. This application claims the benefit of Japanese Patent Application No. 2003-048817 filed Feb. 26, 2003. The disclosures of the above applications are incorporated herein by reference BACKGROUND OF THE INVENTION [0002] 1. Technical Field [0003] The present invention relates to circuit substrates, semiconductor devices, semiconductor manufacturing apparatuses, methods for manufacturing circuit substrates, and methods for manufacturing semiconductor devices, and in particular, is favorably applied to FDB (face down bonding) in COF (chip on film). [0004] 2. Conventional Technology [0005] In conventional semiconductor devices, for example, as described in Japanese Laid-open Patent Application 2001-298046, there is a method to realize FDB in COF through Au-Au bonding by application of heat and pressure. [0006] FIGS. 13(a) and (b) are cross-sectional views showing a conventional method for manufacturing a semiconductor device. [0007] Referring to FIG. 13(a), Cu wiring layers 112 as inner leads are formed on a tape substrate 111, the circumference of the Cu wiring layer 112 is covered by a protection film 113, and exposed portions of the Cu wiring layers 112 are covered by Au plated layers 114. [0008] For example, a polyimide film can be used as the tape substrate 111; and for example, a solder resist can be used as the protection film 113. [0009] On the other hand, pad electrodes 116 are provided on a semiconductor chip 115, the circumference of the pad electrodes 116 is covered by a protection film 117, and Au bump electrodes 118 having a height H2 are formed on the pad electrodes 116. [0010] For example, Al can be used as the pad electrodes 116; and for example, a silicon oxide film or silicon nitride film can be used as the protection film 117. [0011] When the semiconductor chip 115 is mounted on the tape substrate 111the tape substrate 111 is mounted on a bonding stage 101 that is heated, as indicated in FIG. 13(b). Then, while retaining by suction the semiconductor chip by a bonding head 102, the Au bump electrodes 118 are pressed against the Cu wiring layers 112 that are covered by the Au plated layers 114. [0012] When the Au bump electrodes 118 are pressed against the Cu wiring layers 112 that are covered by the Au plated layers 114, the tape substrate 111 below the Au bump electrodes 118 recedes, and a clearance CL2 between edge sections of the semiconductor chip 115 and the Cu wiring layers 112 covered by the Au plated layers 114 is reduced, such that the edge sections of the semiconductor chip 115 may come in contact with the Au plated layers 114. [0013] Accordingly, in the conventional semiconductor device, to prevent the edge sections of the semiconductor chip 115 from contacting the Au plated layers 114, the height H2 of the Au bump electrodes 118 is increased. [0014] For example, when the semiconductor chip 115 is mounted on the tape substrate 111, the clearance CL2 between the edge sections of the semiconductor chip 115 and the Cu wiring layers 112 covered by the Au plated layers 114 becomes to be about 10-12 .mu.m. Accordingly, in order to prevent the edge sections of the semiconductor chip 115 from contacting the Au plated layers 114, the height H2 of the Au bump electrodes 118 is set to about 22.5 .mu.m. [0015] However, increasing the height H2 of the Au bump electrodes 118 leads to an increase in the cost because about 400-500 Au bump electrodes 118 may be provided per semiconductor chip 115, and results in greater variations in the height H2 of the Au bump electrodes 118, which leads to a problem of deteriorated connection reliability of the Au bump electrodes 118 [0016] Accordingly, it is an object of the present invention to provide circuit substrates, semiconductor devices, semiconductor manufacturing apparatuses, methods for manufacturing circuit substrates, and methods for manufacturing semiconductor devices, which can control the height of bump electrodes, and increase the clearance between edge sections of a semiconductor chip and lead terminals of a circuit substrate. SUMMARY [0017] To solve the problems described above, a circuit substrate according to a first aspect is characterized in comprising: a chip mounting region for mounting a chip; a mounting substrate formed to recede at a boundary of the chip mounting region and to incline in a circumference of the chip mounting region; and lead terminals that are formed on the mounting substrate and lay over the chip mounting region. [0018] Accordingly, without increasing the separation between the mounting substrate and the chip surface, the mounting substrate can be kept away from the edge sections of the chip. [0019] Consequently, without increasing the height of the electrodes that connect the chip and the mounting substrate, the edge sections of the chip can be prevented from contacting the mounting substrate, and the connection reliability between the chip and the mounting substrate can be improved. [0020] Also, a semiconductor device according to a second aspect is characterized in comprising: a circuit substrate having lead terminals formed thereon; a semiconductor chip connected to the lead terminals through bump electrodes; a concave section that is provided in the circuit substrate and disposed at a position corresponding to an edge position of the semiconductor chip; and an inclined section that is provided by inclining the mounting substrate in an outer circumferential section of the edge position. [0021] Accordingly, the circuit substrate can be curved and bent in a manner that the circuit substrate extends away from the edge section of the semiconductor chip, and the edge section of the semiconductor chip can be prevented from contacting the circuit substrate without increasing the height of the bump electrodes. Continue reading about Circuit substrates, semiconductor devices, semiconductor manufacturing apparatuses, methods for manufacturing circuit substrates, and methods for manufacturing semiconductor devices... Full patent description for Circuit substrates, semiconductor devices, semiconductor manufacturing apparatuses, methods for manufacturing circuit substrates, and methods for manufacturing semiconductor devices Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Circuit substrates, semiconductor devices, semiconductor manufacturing apparatuses, methods for manufacturing circuit substrates, and methods for manufacturing semiconductor devices patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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