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  Circuit board structure and method for fabricating the sameRelated Patent Categories: Electrolysis: Processes, Compositions Used Therein, And Methods Of Preparing The Compositions, Electrolytic Coating (process, Composition And Method Of Preparing Composition), Coating Selected Area, Specified Product Produced, Product Is Circuit Board Or Printed CircuitThe Patent Description & Claims data below is from USPTO Patent Application 20070017815. Brief Patent Description - Full Patent Description - Patent Application Claims
BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] This invention relates to a circuit board structure and a method for fabricating the same, and more particularly, to a circuit board structure integrated with heat sinks and a method for fabricating the same. [0003] 2. Description of Related Art [0004] With the rapid development of electronic industry, modern electronic products have various functions and better performance. In order to meet the requirements of small dimension but high integration for a semiconductor chip, a circuit board, which is used for carrying a plurality of active and passive components, is changed from having only one layer to having multiple layers. [0005] However, such a small-dimensiond but highly integrated semiconductor chip generates considerate amount of heat, which easily overheats or even makes unrecoverable damage on the semiconductor chip [0006] Adhering a plurality of heat dissipating spreaders onto the circuit board is one of the most popular ways to dissipate the heat generated by the semiconductor chip. Please refer to FIG. 1, which is a cross sectional view of a cavity-down ball grid array (CDBGA) package structure 10 according to the prior art. The package structure comprises a circuit board 11, a cavity 113 formed on the circuit board 11, a heat dissipating spreader 12 adhered to a first surface 11a of the circuit board 11, a semiconductor chip 13 held in the cavity 113 and on the heat dissipating spreader 12. The heat dissipating spreader 12 comprises a high heat conductivity material such as copper. The semiconductor chip 13 comprises an active surface 13a and an inactive surface 13b. In a process to assembly the package structure 10, the semiconductor chip 13 is disposed in the cavity 113 of the circuit board 11, a non-electrically active surface 13b is adhered to the heat dissipating spreader 12, a plurality of solder pads 17 are disposed on a second surface 11b of the circuit board 11, a plurality of arc solder wires 14 are formed by a solder wire process to electrically connect the semiconductor chip 13 to a plurality of electrically conductive pads 114 disposed on the second surface 11b of the circuit board 11, an encapsulant 15 is formed by an encapsulant process to covering the semiconductor chip 13 and the arc solder wires 14, and a plurality of solder balls 16 are implanted by a ball implanting process on the second surface 11b of the circuit board 11. [0007] Although the heat dissipating spreader 12 can effectively dissipate heat generated by the semiconductor chip 13, the solder balls 16 have to be disposed higher than the arc solder wires 14 to ensure the solder balls can be soldered to the external electronic device such as a printed circuit board, this affecting a layout of the circuit board 11. Moreover, the arc solder wires near the semiconductor chip 13 are crowded and easily short to each other. Further, in the encapsulant process, the circuit board 11, on which the semiconductor chip 13 and the arc solder wires 14 are already disposed, is placed in a package mold, and then epoxy resin is injected into the mold to form the encapsulant 15 for covering the semiconductor chip 13 and the arc solder wires 14. However, the semiconductor chip 13 generally does not fit the mold and will not be fixed in the mold tightly and closely, so the epoxy resin is easily injected to a region outside of the mold and part of the encapsulant 15 are formed on the second surface 11b of the circuit board 11. In result, the package structure 10 is uneven and looks untidy and some of the solder pads 17 may get contaminated, affecting the electrical conductive quality of the package structure 10 because the contaminated solder pads 17 and the solder balls 16 thereon can not be conductive tightly. Moreover, the epoxy resin a kind of fluid, and affects the electrical conductive between the semiconductor chip 13 and the circuit board 11 when injected into the mold. If the epoxy resin is injected excessively in terms of quantity and speed into the mold, the arc solder wires 16 will be drawn too close or even contact to each other, resulting in a short problem and degrading the package structure 10. [0008] Moreover, adhering the heat dissipating spreader 12 onto the circuit board 11 increases the thickness of the package structure 10, which is contradictory to a development trend that a modern electronic device is required to have varieties of functions and compact dimension. [0009] Therefore, how to provide a circuit board structure having well heat dissipating capability, to solve the drawbacks of the prior art that the package structure 10 has too big the dimension because the heat dissipating spreader 12 is adhered to the circuit board 11, has becoming one of the urgent errands in the art. SUMMARY OF THE INVENTION [0010] In views of the above-mentioned problems of the prior art, it is a primary objective of the present invention to provide a circuit board structure and a method fabrication the same, for providing a chip disposed on the circuit board structure a well heat dissipating path and reducing the dimension of a circuit board. [0011] To achieve the above-mentioned and other objectives, a circuit board structure and a method for fabricating the same are provided according to the present invention. The method includes forming on a carrier board a plurality of conductive bumps and first solder masks filled in gaps between the conductive bumps for exposing the conductive bumps; forming on the first solder masks and the conductive bumps a conductive layer and on the conductive layer a first resistive layer having a plurality of openings for exposing part of the conductive layer; forming in the openings of the first resistive layer a first circuit layer and a first heat sink; forming on the first heat sink, the first resistive layer and the first circuit layer a second resistive layer having a plurality of openings for exposing the first heat sink; forming a second heat sink on the first heat sink exposed to a region outside of the openings of the second resistive layer; removing the second resistive layer, the first resistive layer and the conductive layer covered by the first resistive layer, and forming a dielectric layer on the first circuit layer and the first solder mask where neither the first heat sink nor the second heat sink is formed; and forming on the second heat sink a third heat sink, and forming on the dielectric layer a second circuit layer electrically conductive to the first circuit layer. [0012] The method further includes removing the carrier board. The method further includes forming on the second circuit layer a second solder mask having a plurality of openings for exposing an electrically conductive pads of the second circuit layer. The method further includes performing a circuit build-up process on the second circuit layer to form a circuit build-up structure. [0013] The circuit board structure fabricated by the method includes a dielectric layer having a first surface and a second surface; a plurality of heat sinks embedded in the dielectric layer and protruding to a region above the second surface of the dielectric layer; a first circuit layer embedded in the dielectric layer and disposed evenly with the first surface of the dielectric layer; and a second circuit layer formed on the second surface of the dielectric layer second surface and electrically conductive to the first circuit layer, wherein the first circuit layer is electrically conductive by a conductive via formed in the dielectric layer to the second circuit layer. [0014] The circuit board structure further includes a first solder mask formed on the first surface of the dielectric layer and having a plurality of openings for exposing part of the first circuit layer, a plurality of conductive bumps formed in the openings of the first solder mask, and a second solder mask formed on the second circuit layer and having a pluralities of openings for exposing the electrically conductive pads of the second circuit layer. [0015] Compared with the prior art, the circuit board structure and the method for fabricating the same integrate the heat sinks directly into the circuit board, which already has the first circuit layer, the dielectric layer and the second circuit layer. Therefore, the circuit board of the present invention is thin and can be applied to a modern electronic device required to be minimization. [0016] Moreover, embedded with heat sinks, the circuit board needs not to reserve a certain space for the installation of the heat sinks and has a larger circuit layout space, so as to overcome the drawback of the prior art that the circuit board does not have a big layer space because a certain space on the circuit board has to be reserved for a heat dissipating spreader ready to be adhered to the circuit board. [0017] Further, in the present invention the heat sinks are integrated into the circuit board to for a circuit board structure having well heat dissipating capability, such that heat dissipated by a semiconductor chip disposed on the heat sinks can be conducted over the heat sinks. A circuit build-up layer can be further formed on the circuit board structure of the present invention, so as to form a multi-layered circuit structure. BRIEF DESCRIPTION OF DRAWINGS [0018] The invention can be more fully understood by reading the following detailed description of the preferred embodiments, with reference made to the accompanying drawings, wherein: [0019] FIG. 1 is a cross sectional view of a cavity-down ball grid array (CDBGA) package structure 10 according to the prior art; [0020] FIG. 2A-2J are ten cross sectional views demonstrating a method for fabricating a circuit board structure of a first embodiment according to the present invention; and [0021] FIGS. 3A and 3B are two cross sectional views demonstrating a method for fabricating a circuit board structure of a second embodiment according to the present invention. Continue reading... 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