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Chun-Hsiung Hung patents

Recent bibliographic sampling of Chun-Hsiung Hung patents listed/published in the public domain by the USPTO (USPTO Patent Application #,Title):



04/09/15 - 20150100852 - Ecc method for double pattern flash memory
A method of operating a memory device storing ECCs for corresponding data is provided. The method includes writing an extended ECC during a first program operation, the extended ECC including an ECC and an extended bit derived from the ECC. The method includes overwriting the extended ECC with a pre-determined...
Inventors: Shih-chang Huang, Ken-hui Chen, Chun-hsiung Hung (Macronix International Co., Ltd.)

03/26/15 - 20150085588 - Method and apparatus for adjusting drain bias of a memory cell with addressed and neighbor bits
The storage layer such as a nitride layer of a nonvolatile memory cell has two storage parts storing separately addressable data, typically respectively proximate to the source terminal and the drain terminal. The applied drain voltage while sensing the data of one of the storage parts depends on the data...
Inventors: Han-sung Chen, Chung-kuang Chen, Chun-hsiung Hung (Macronix International Co., Ltd.)

03/05/15 - 20150063023 - Plural operation of memory device
An integrated circuit device comprises a semiconductor substrate, a first memory block on the substrate comprising NAND memory cells, a second memory block on the substrate comprising NAND memory cells, and controller circuitry. The first and second memory blocks are configurable to store data for a first pattern of data...
Inventors: Tzung Shen Chen, Shuo Nan Hong, Yi Ching Liu, Chun-hsiung Hung (Macronix International Co., Ltd.)

02/26/15 - 20150055412 - Method and apparatus for reducing erase disturb of memory by using recovery bias
A nonvolatile memory array is divided into multiple memory groups. The nonvolatile memory array receives an erase command to erase a first set of the memory groups, and not a second set of the memory groups. The control circuitry is responsive to the erase command to erase the first set...
Inventors: Chun-hsiung Hung, Bo-chang Wu, Kuen-lung Chang, Ken-hui Chen (Macronix International Co., Ltd.)

12/11/14 - 20140361824 - Clock integrated circuit
The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise....
Inventors: Chung-kuang Chen, Chun-hsiung Hung, Han-sung Chen (Macronix International Co., Ltd.)

09/18/14 - 20140281175 - Program method, data recovery method, and flash memory using the same
A program method for a multi-level cell (MLC) flash memory is provided. The memory array includes a plurality of pages and a plurality of paired pages, which correspond to the respective pages. The program method includes the following steps. Firstly, a program address command is obtained. Next, whether the program...
Inventors: Lung-yi Kuo, Hsin-yi Ho, Chun-hsiung Hung, Shuo-nan Hung, Han-sung Chen (Macronix International Co., Ltd.)

09/18/14 - 20140281150 - Difference l2p method
A method for maintaining a data set includes storing a base copy of the data set in a first non-volatile memory having a first writing speed, storing changes to the data set in a first change data set in a second non-volatile memory having a second writing speed, and generating...
Inventors: Lung-yi Kuo, Hsin-yi Ho, Chun-hsiung Hung, Han-sung Chen

09/18/14 - 20140269127 - Memory operation latency control
An integrated circuit with memory can operate with reduced latency between consecutive operations such as read operations. At a first time, a first operation command is finished on a memory array on an integrated circuit. At a second time, a second operation command is begun on the memory array. A...
Inventors: Chun-hsiung Hung, Han Sung Chen, Ming Chao Lin (Macronix International Co., Ltd.)

09/11/14 - 20140258811 - Storage scheme for built-in ecc operations
A device includes a memory array storing data and error correcting codes ECCs corresponding to the data, and a multi-level buffer structure between the memory array and an input/output data path. The memory array includes a plurality of data lines for page mode operations. The buffer structure includes a first...
Inventors: Yi-ching Liu, Chi Lo, Shuo-nan Hung, Chun-hsiung Hung (Macronix International Co., Ltd.)

09/11/14 - 20140258794 - Memory page buffer
Counting status circuits are electrically coupled to corresponding status elements. The status elements selectably store a bit status of a bit line coupled to a memory array. The bit status can indicate one of at least pass and fail. The counting status circuits are electrically coupled to each other in...
Inventors: Yih-shan Yang, Shou-nan Hung, Chun-hsiung Hung, Yao-jen Kuo, Meng-fan Chang (Macronix International Co., Ltd.)

09/11/14 - 20140254297 - Method and apparatus for memory repair
An integrated circuit includes an array of memory cells that is arranged into rows, main columns, and redundant columns that perform repairs in the array. The main columns and the redundant columns are divided into row blocks. Bit lines couple the main columns to status memory indicating repair statuses of...
Inventors: Shuo-nan Hung, Chi Lo, Chun-hsiung Hung (Macronix International Co., Ltd.)

09/11/14 - 20140254284 - Word line driver circuit for selecting and deselecting word lines
A memory circuit includes word lines coupled to a memory array, including a first set of one or more word lines deselected in an erase operation, and a second set of one or more word lines selected in the erase operation. Control circuitry couples the first set of one or...
Inventors: Chun-hsiung Hung, Ti Wen Chen, Shuo-nan Hung, Shih-lin Huang (Macronix International Co., Ltd.)

08/28/14 - 20140241070 - Reference and sensing with bit line stepping method of memory
A sensing method for a memory is provided. The memory includes: a memory cell; a reference circuit generating a reference voltage and a clamp voltage; and a current supplying circuit receiving the clamp voltage to develop a cell current passing through the memory cell to form a cell voltage, wherein...
Inventors: Tien-yen Wang, Chun-hsiung Hung, Chia-jung Chen

07/31/14 - 20140210522 - Drive circuitry compensated for manufacturing and environmental variation
Current drivers and biasing circuitry at least partly compensate for manufacturing variations and environmental variations such as supply voltage, temperature, and fabrication process....
Inventors: Shang-chi Yang, Ken-hui Chen, Su-chueh Lo, Kuen-long Chang, Chun-hsiung Hung

05/29/14 - 20140146611 - Memory device and method for programming memory cell of memory device
A method for programming a memory cell of a memory device includes the following steps. A plurality of cycle number ranges are set up. A specific one of the plurality of cycle number ranges, in which the memory cell having a drain terminal passes a program-verification, is determined. A bias...
Inventors: Chung-kuang Chen, Han-sung Chen, Chun-hsiung Hung (Macronix International Co., Ltd.)

05/22/14 - 20140141583 - Memory architecture of 3d array with diode in memory string
A 3D memory device includes a plurality of ridge-shaped stacks, in the form of multiple strips of conductive material separated by insulating material, arranged as strings which can be coupled through decoding circuits to sense amplifiers. Diodes are connected to the bit line structures at either the string select of...
Inventors: Chun-hsiung Hung, Shin-jang Shen, Hang-ting Lue (Macronix International Co., Ltd.)

03/13/14 - 20140075265 - Outputting information of ecc corrected bits
The present invention provides a method of operating a memory device storing error correcting codes ECCs for corresponding data and including ECC logic to correct errors using the ECCs. The method includes correcting data using ECCs for the data on the memory device, and producing information on the memory device...
Inventors: Chun-hsiung Hung, Hsin Yi Ho (Macronix International Co., Ltd.)

02/27/14 - 20140055187 - Clock integrated circuit
The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise....
Inventors: Chung-kuang Chen, Chun-hsiung Hung, Han-sung Chen (Macronix International Co., Ltd.)

01/23/14 - 20140021935 - Voltage buffer apparatus
The present invention relates to an apparatus of bandgap buffer which comprising a voltage processing module to produce a bandgap buffer voltage in response to an input voltage and a feedback signal and a symmetry circuit coupled to the voltage processing module for producing the feedback signal and regulating the...
Inventors: Chun-hsiung Hung, Ju-an Chiang (Macronix International Co., Ltd.)

12/05/13 - 20130326184 - Memory apparatus
A memory apparatus includes a host device and a slave device. The host device stores verification data. The slave device includes a memory unit, a control unit, and a logic unit. The control unit drives the memory unit to provide storage data in a data transmission sub-period, and further provides...
Inventors: Yu-meng Chaung, Chun-hsiung Hung, Kuen-long Chang, Ken-hui Chen, Nai-ping Kuo (Macronix International Co., Ltd.)

11/28/13 - 20130314997 - Memory access method and flash memory using the same
A memory access method is applied in a memory controller for accessing a memory array, including a number of respective select switches globally controlled with a string select signal. The memory access method includes: enabling the string select signal and disabling the string select signal before a read phase....
Inventors: Chung-kuang Chen, Shuo-nan Hung, Chun-hsiung Hung (Macronix International Co., Ltd.)

11/07/13 - 20130294173 - Method and apparatus for the erase suspend operation
Various aspects of a nonvolatile memory have an improved erase suspend procedure. A bias arrangement is applied to word lines of an erase sector undergoing an erase procedure interrupted by an erase suspend procedure. As a result, another operation performed during erase suspend, such as a read operation or program...
Inventors: Chuan-ying Yu, Ken-hui Chen, Chun-hsiung Hung, Kuen-long Chang

11/07/13 - 20130294155 - Plural operation of memory device
An integrated circuit device comprises a semiconductor substrate, a first memory block on the substrate comprising NAND memory cells, a second memory block on the substrate comprising NAND memory cells, and controller circuitry. The first and second memory blocks are configurable to store data for a first pattern of data...
Inventors: Tzung-shen Chen, Shuo-nan Hong, Yi-ching Liu, Chun-hsiung Hung

10/31/13 - 20130286744 - Bit line bias circuit with varying voltage drop
A bit line bias circuit of a memory architecture includes a varying voltage drop. In some embodiments, the voltage drop can depend on the threshold voltage of the memory cell selected to be read, or on the sense current flowing through the memory cell selected to be read....
Inventors: Chung-kuang Chen, Han-sung Chen, Chun-hsiung Hung (Macronix International Co., Ltd.)

10/31/13 - 20130285737 - Charge pump system
In one aspect, a first charge pump has serially arranged charge pump stages. Inter-stage nodes between adjacent stages are pumped by a second charge pump. In another aspect, timing of the charge pump stages is controlled by at a command clock signal. The command clock signal and command data are...
Inventors: Yung Feng Lin, Chun-jen Huang, Tzeng-huei Shiau, Chun-hsiung Hung, Caiyun Wu, Qifang Wang (Macronix International Co., Ltd.)

09/12/13 - 20130235674 - Memory page buffer
Various embodiments address various difficulties with source side sensing difficulties in various memory architectures, such as 3D vertical gate flash and multilevel cell memory. One such difficulty is that with source side sensing, the signal amplitude is significantly smaller than drain side sensing. Another such difficulty is the noise and...
Inventors: Chun-hsiung Hung, Chi Lo (Macronix International Co., Ltd.)

08/22/13 - 20130215687 - Method and apparatus for dynamic sensing window in memory
A memory array is characterized by a threshold definition, which includes threshold voltage ranges representing data values stored by a part of the memory array, and a set of sense windows separating the threshold voltage ranges. The threshold definition is varied, responsive to at least one of program operations and...
Inventors: Han-sung Chen, Chung-kuang Chen, Chun-hsiung Hung (Macronix International Co., Ltd.)

08/22/13 - 20130214820 - Apparatus and method to tolerate floating input pin for input buffer
An integrated circuit device includes a pad adapted to receive a signal from an internal or external driver, and an input buffer circuit including an input terminal coupled to the pad. The input buffer circuit includes a pass transistor having a control terminal, a first conduction terminal connected to the...
Inventors: Chun-hsiung Hung, Kuen-long Chang, Nai-ping Kuo, Ming-chih Hsieh

08/15/13 - 20130208552 - Method and apparatus for adjusting drain bias of a memory cell with addressed and neighbor bits
The storage layer such as a nitride layer of a nonvolatile memory cell has two storage parts storing separately addressable data, typically respectively proximate to the source terminal and the drain terminal. The applied drain voltage while sensing the data of one of the storage parts depends on the data...
Inventors: Han-sung Chen, Chung-kuang Chen, Chun-hsiung Hung (Macronix International Co., Ltd.)

06/13/13 - 20130148445 - Local word line driver
A memory circuit with a word line driver and control circuitry is disclosed. The plurality of word line drivers are coupled to a plurality of word lines. Word line drivers include a CMOS inverter, which can have an input and an output, and a p-type transistor and an n-type transistor....
Inventors: Chung-kuang Chen, Han-sung Chen, Chun-hsiung Hung

06/06/13 - 20130145201 - Automatic internal trimming calibration method to compensate process variation
A method is described for performing an automatic internal trimming operation that can compensate process variation and supply voltage variation in an integrated circuit. A reference signal is applied when the integrated circuit is in an automatic internal trimming mode, and integrated circuit timing is trimmed into a predetermined target...
Inventors: Chih-ting Hu, Ken-hui Chen, Chun-hsiung Hung (Macronix International Co., Ltd.)

05/23/13 - 20130128670 - Memory access method and flash memory using the same
A memory access method is applied in a memory controller for accessing an NAND memory array, including a number of respective select switches globally controlled with a string select signal. The memory access method includes the following steps. A stream bias signal and a selected word line signal are respectively...
Inventors: Chung-kuang Chen, Shuo-nan Hung, Chun-hsiung Hung (Macronix International Co., Ltd.)

05/02/13 - 20130107637 - Memory program discharge circuit of bit lines with multiple discharge paths
A memory integrated circuit has an array of nonvolatile memory cells, bit lines accessing the array of nonvolatile memory cells, and bit line discharge circuitry. The bit lines have multiple discharge paths for a bit line at a same time, during a program operation....
Inventors: Chung-kuang Chen, Han-sung Chen, Chun-hsiung Hung

04/25/13 - 20130100758 - Local word line driver
A memory circuit with a word line driver and control circuitry is disclosed. The word line driver receives a first voltage reference signal, a second voltage reference signal, and an input signal. The word line driver has an output coupled to a word line. The control circuitry is configured to...
Inventors: Han-sung Chen, Chun-hsiung Hung, Chung-kuang Chen

04/25/13 - 20130100745 - Method and apparatus of performing an erase operation on a memory integrated circuit
Various discussed approaches include an improved grouping of edge word lines and center word lines of an erase group during erase verify and erase sub-operations of an erase operation. In another approach, changed voltage levels of edge word lines to address the over-erase issue of the erase group, and also...
Inventors: Yi-fan Chang, Cheng Ming Yih, Su-chueh Lo, Jian Shing Liu, Kuen Long Chang, Chun-hsiung Hung

04/18/13 - 20130094319 - Method and apparatus of addressing a memory integrated circuit
A memory integrated circuit has control circuitry that accesses memory cells of the memory integrated circuit. The control circuitry is responsive to commands including a first command and a second command. The first command specifies a high order set of address bits. The second command specifies a low order set...
Inventors: Chun-hsiung Hung, Kuen-long Chang, Hsieh Ming Chih

12/27/12 - 20120327722 - Method and system for a serial peripheral interface
An integrated circuit includes a serial peripheral interface memory device. In an embodiment, the memory device includes a clock signal, a plurality of pins, and a configuration register. In an embodiment, the configuration register includes a wait cycle count. The method includes transmitting a read address to the memory device...
Inventors: Chun-hsiung Hung, Kuen-long Chang, Chia-he Liu (Macronix International Co., Ltd.)

12/20/12 - 20120319756 - Clock integrated circuit
The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise....
Inventors: Chung-kuang Chen, Chun-hsiung Hung, Han-sung Chen (Macronix International Co., Ltd.)

11/29/12 - 20120300553 - Method and apparatus of performing an erase operation on a memory integrated circuit
Various discussed approaches improve the over erase issue and the coupling effect, and include (A) multilevel contacts between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line; (B) a sufficient...
Inventors: Yi-fan Chang, Su-chueh Lo, Cheng Ming Yih, Ta Kang Chu, Chu Ching Wu, Kuo Yu Liao, Ken Hui Chen, Kuen-long Chang, Chun-hsiung Hung (Macronix International Co., Ltd.)

11/08/12 - 20120281471 - Memory page buffer
Various embodiments address various difficulties with source side sensing difficulties in various memory architectures, such as 3D vertical gate flash and multilevel cell memory. One such difficulty is that with source side sensing, the signal amplitude is significantly smaller than drain side sensing. Another such difficulty is the noise and...


10/18/12 - 20120265923 - Program method, data recovery method, and flash memory using the same
A program method for a multi-level cell (MLC) flash memory is provided. The memory array includes a plurality of pages and a plurality of paired pages, which correspond to the respective pages. The program method includes the following steps. Firstly, a program address command is obtained. Next, whether the program...


10/18/12 - 20120262988 - Method and apparatus for leakage suppression in flash memory
Techniques are described herein for detecting and recovering over-erased memory cells in a flash memory device. In one embodiment, a flash memory device is described including a memory array including a plurality of blocks of memory cells. The device also includes a controller to perform a leakage-suppression process. The leakage-suppression...


10/18/12 - 20120262987 - Method and apparatus for leakage suppression in flash memory in response to external commands
Techniques are described herein for detecting and recovering over-erased memory cells in a flash memory device. In one embodiment, a flash memory device includes a memory array including a plurality of blocks of memory cells. The device also includes a command interface to receive a command from a source external...


09/06/12 - 20120224443 - Sense amplifier with shielding circuit
A sense amplifier includes a first transistor, a second transistor, an output circuit, and a shielding circuit. The first transistor has a gate bias established by a cell current, and the second transistor has a gate bias established by a reference current. The output circuit is coupled to the first...


08/02/12 - 20120198298 - On-the-fly repair method for memory
An on-the-fly repair method for a memory includes: performing a block erase operation on the memory; checking whether the block erase operation is passed or not; finding whether there is any available and healthy redundancy block in the memory if the block erase operation is not passed; programming an address...


04/19/12 - 20120092937 - Method and system for a serial peripheral interface
A method for dual I/O data read in an integrated circuit which includes a serial peripheral interface memory device. In an embodiment, the memory device includes a clock signal, a plurality of pins, and a configuration register. In an embodiment, the configuration register includes a wait cycle count. The method...


03/15/12 - 20120063232 - Method and apparatus for reducing read disturb in memory
Various aspects of a NAND memory include have multiple versions of a high threshold voltage distribution—a version with a reduced maximum, and another version. The version with a reduced maximum has a reduced word line pass voltage....


03/01/12 - 20120051137 - Memory architecture of 3d array with diode in memory string
A 3D memory device includes a plurality of ridge-shaped stacks, in the form of multiple strips of conductive material separated by insulating material, arranged as strings which can be coupled through decoding circuits to sense amplifiers. Diodes are connected to the bit line structures at either the string select of...


01/26/12 - 20120019232 - Current source with tunable voltage-current coefficient
A current source providing an output current with a fixed current range includes a bias circuit, a resistor, a current mirror, and a controller. The bias circuit provides a first voltage weighted with a first tunable coefficient and a second voltage weighted with a second tunable coefficient. The resistor has...


01/12/12 - 20120007167 - 3d memory array with improved ssl and bl contact layout
A 3D memory device includes a plurality of ridges, in some embodiments ridge-shaped, in the form of multiple strips of conductive material separated by insulating material, arranged as bit lines which can be coupled through decoding circuits to sense amplifiers. The strips of conductive material have side surfaces on the...


09/01/11 - 20110210776 - Clock integrated circuit
The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise....


06/30/11 - 20110161750 - Pre-code device, and pre-code system and pre-coding method thereof
A pre-code device includes firstly memory circuit, an address decoder, and an alternative logic circuit. The first memory circuit includes a number of memory blocks and at east a replacing block. The memory blocks are pointed by a number of respective physical addresses. The replacing block is pointed by a...


06/23/11 - 20110149669 - Sense amplifier and data sensing method thereof
A data sensing method for sensing storage data stored in a memory cell includes the steps of: biasing a sensing node and a reference node to a first voltage in response to a first control signal; discharging the sensing node and the reference node via the memory cell and a...


06/09/11 - 20110138216 - Clock integrated circuit
The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise....


06/09/11 - 20110138213 - Clock integrated circuit
The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise....


06/09/11 - 20110133804 - Clock integrated circuit
The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise....


05/26/11 - 20110122721 - Y-decoder and decoding method thereof
A Y-decoder includes a selection unit and a Y-MUX. The selection unit is coupled to the memory array for selecting the column lines. The Y-MUX is coupled to the selection unit for supplying a voltage to the selected column line. The Y-MUX includes a first switch, a second switch, a...


03/24/11 - 20110069571 - Word line decoder circuit apparatus and method
One embodiment of the technology is an apparatus, a memory integrated circuit. The memory integrated circuit has word line address decoding circuitry. The circuit allows selection of a single word line to have an erase voltage. A decoder circuit includes an inverter and logic. The inverter has an input, and...


03/24/11 - 20110069544 - Method and apparatus for programming a multi-level memory
A method of programming a memory device comprising a plurality of memory cells may include verifying a first memory cell targeted to a first level with a first preliminary voltage of a first program phase (PPV1′), programming the first memory cell targeted to the first level in the first program...


03/10/11 - 20110060962 - Method and apparatus for accessing memory with read error by changing comparison
In response to a disagreement between a previously generated check code associated with previously programmed data bits and a more recently generated check code generated in response to a read command, the comparison process is changed, between i) a value representing accessed data and ii) a reference applied to such...


01/27/11 - 20110019487 - Apparatus and method for detecting word line leakage in memory devices
According to an embodiment of the present invention, a method for detecting word line leakage in a memory device includes coupling a first word line in the memory device to a voltage source while coupling a second word line in the memory device to a ground level voltage. Next, the...


01/27/11 - 20110019473 - Memory array and method of operating one of a plurality of memory cells
An embodiment of the invention provides a memory array including a plurality of bit lines, a plurality of memory cells and a device. Each of the plurality of memory cells has a first node, a second node and a third node, wherein the third node is coupled to one of...


01/27/11 - 20110019456 - Sense amplifier with shielding circuit
A sense amplifier comprises a sense node, a reference node, a memory input stage circuit, a reference input stage circuit, an output stage circuit, and a shielding circuit. The memory input stage circuit comprises first input node for maintaining a first sense voltage established by a cell current and establishes...


01/20/11 - 20110016291 - Serial memory interface for extended address space
An integrated circuit memory device has a memory array and control logic with at least a first addressing mode in which the instruction includes a first instruction code and an address of a first length; and a second addressing mode in which the instruction includes the first instruction code and...


12/02/10 - 20100301918 - Level shifter and level shifting method thereof
A level shifter includes a first level-switching device and a second level-switching device. The first level-switching device includes a first switch device, a second switch device, a first control switch and a third switch device. The first switch device is for receiving the input voltage and outputting a first voltage....


07/22/10 - 20100182842 - Sense amplifier and data sensing method thereof
A data sensing method for sensing data stored in first and second memory cells includes the steps of: setting a first voltage according to a bit-line voltage corresponding to the first memory cell in response to an enabled level of a first clock signal; providing the first voltage as a...


04/29/10 - 20100103738 - Memory and operating method thereof
A method of programming data stored in a memory, which comprises a number of user-defined blocks, a number of manufacture-defined blocks, and an information block, includes the following steps. A programming address pointing to a user-defined block in the memory and programming data is obtained. After that, it is determined...


04/01/10 - 20100082880 - Pre-code device, and pre-code system and pre-coding method thererof
A pre-code device includes firstly memory circuit, an address decoder, and an alternative logic circuit. The first memory circuit includes a number of memory blocks and at east a replacing block. The memory blocks are pointed by a number of respective physical addresses. The replacing block is pointed by a...


03/11/10 - 20100061174 - Y-decoder and decoding method thereof
AY-decoder includes a selection unit and a Y-MUX. The selection unit is coupled to the memory array for selecting the column lines. The Y-MUX is coupled to the selection unit for supplying a voltage to the selected column line. The Y-MUX includes a first switch, a second switch, a third...


03/04/10 - 20100054045 - Memory and reading method thereof
A memory includes many memory regions each including a target memory cell, a source line, a bit line and a reading control circuit. The source line is coupled to a first terminal of the target memory cell. The bit line is coupled to a second terminal of the target memory...


01/14/10 - 20100007380 - Level shifter and level shifting method thereof
A level shifter includes a first level-switching device and a second level-switching device. The first level-switching device includes a first switch device, a second switch device, a first control switch and a third switch device. The first switch device is for receiving the input voltage and outputting a first voltage....


12/17/09 - 20090310423 - Method of programming and erasing a non-volatile memory array
A method of processing an array of non-volatile memory cells to program or erase the same, by applying a voltage to the same through a program and verify pulse application circuit. The process includes a first step of selecting a voltage to be applied. Then, the maximum number of memory...


12/03/09 - 20090296506 - Sense amplifier and data sensing method thereof
A data sensing method for sensing storage data stored in a memory cell includes the steps of: biasing a sensing node and a reference node to a first voltage in response to a first control signal; discharging the sensing node and the reference node via the memory cell and a...


11/05/09 - 20090273999 - Sense amplifier and data sensing method thereof
A data sensing method for sensing data stored in first and second memory cells includes the steps of: setting a first voltage according to a bit-line voltage corresponding to the first memory cell in response to an enabled level of a first clock signal; providing the first voltage as a...


09/10/09 - 20090225607 - Apparatus and method for detecting word line leakage in memory devices
Some embodiments of the present invention provide a memory device including a first memory array having a first word line and a comparator circuit having a first terminal coupled to a reference voltage and a second terminal coupled to a first switch selectively coupling the first word line to a...


09/10/09 - 20090225605 - Nitride read-only memory cell and nitride read-only memory array
A NROM memory device includes an array of memory cells and first and second bit lines. The first and second bit lines are coupled to opposite sides of the memory cells. During an erase operation, one of the sides of the memory cells receives a positive voltage and the other...


08/13/09 - 20090201731 - Method and apparatus for accessing memory with read error by changing comparison
In response to a disagreement between a previously generated check code associated with previously programmed data bits and a more recently generated check code generated in response to a read command, the comparison process is changed, between i) a value representing accessed data and ii) a reference applied to such...


06/11/09 - 20090147799 - Circuit and method for transmitting data stream
A circuit including a first data selection circuit and a second data selection circuit for transmitting a data stream is provided. The first data selection circuit having first controllable channels turns on a first operating channel being one of the first controllable channels in an odd-numbered period and turns off...


05/14/09 - 20090121780 - Multiple-stage charge pump with charge recycle circuit
A multiple-stage charge pump circuit comprises first and second pump capacitors, first and second transfer circuits, first and second driving circuits, and a charge recycle circuit. The first pump capacitor, the first transfer circuit, and the first driving circuit form a first stage circuit and the second pump capacitor, the...


03/05/09 - 20090063918 - Apparatus and method for detecting word line leakage in memory devices
A method for detecting word line leakage in a memory device includes coupling a first plurality of word lines in the memory device to a voltage source while grounding a second plurality of word lines. Each of the second plurality of word lines is adjacent to a corresponding one of...


02/19/09 - 20090046521 - Memory structure, programming method and reading method therefor, and memory control circuit thereof
The memory structure improves a sensing accuracy of memory cells by dividing the main array into a number of memory units and sensing memory cells of each memory units with an appropriate set of reference currents. Each of the memory units corresponds to a reference group bit value, which indicates...


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Archived*
(*May have duplicates - we are upgrading our archive.)

20120327722 - Method and system for a serial peripheral interface


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The bibliographic references displayed about Chun-Hsiung Hung's patents are for a recent sample of Chun-Hsiung Hung's publicly published patent applications. The inventor/author may have additional bibliographic citations listed at the USPTO.gov. FreshPatents.com is not associated or affiliated in any way with the author/inventor or the United States Patent/Trademark Office but is providing this non-comprehensive sample listing for educational and research purposes using public bibliographic data published and disseminated from the United States Patent/Trademark Office public datafeed. This information is also available for free on the USPTO.gov website. If Chun-Hsiung Hung filed recent patent applications under another name, spelling or location then those applications could be listed on an alternate page. If no bibliographic references are listed here, it is possible there are no recent filings or there is a technical issue with the listing--in that case, we recommend doing a search on the USPTO.gov website.

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