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  Chip having timing analysis of paths performed within the chip during the design processUSPTO Application #: 20080052655Title: Chip having timing analysis of paths performed within the chip during the design process Abstract: An integrated circuit chip is made using Genie, a described computer chip design tool which can analyze the data contained within an entire endpoint report, compute relationships between paths based on shared segments, and display this information graphically to the designer. Specifically, Genie groups failing paths into Timing Islands. A timing island is a group of paths which contain at least one shared segment. The most frequently shared segment is sifted to the top of the priority list for each island, and is labeled as the Hub. Thinking of timing islands as a tree, the hub of the island would be the trunk. If you chop the tree down by the trunk, all of the branches, limbs and twigs will fall down too. This is analogous to fixing the timing failures in the hub, and the fix trickling out to each of the segments that dangle off the hub. (end of abstract) Agent: International Business Machines Corporation - Poughkeepsie, NY, US Inventors: James J. Curtin, Michael J. Cadigan, Edward J. Hughes, Kevin M. Mcllvain, Jose L. Neves, Ray Raphy, Douglas S. Search USPTO Applicaton #: 20080052655 - Class: 716006000 (USPTO) Related Patent Categories: Data Processing: Design And Analysis Of Circuit Or Semiconductor Mask, Circuit Design, Testing Or Evaluating, Design Verification (e.g., Wiring Line Capacitance, Fan-out Checking, Minimum Path Width), Timing Analysis (e.g., Delay Time, Path Delay, Latch Timing) The Patent Description & Claims data below is from USPTO Patent Application 20080052655. Brief Patent Description - Full Patent Description - Patent Application Claims
[0001] This application is a continuation of U.S. Ser. No. 11/729784 which in turn is a continuation in part of U.S. Ser. No. 10/890463, filed Jul. 12, 2004, and entitled "Method, System and Storage Medium for Determining Circuit Placement" by James Curtin et al., and contains subject matter which is related to the subject matter of the following co-pending applications, each of which is assigned to the same assignee as this application, International Business Machines Corporation of Armonk, N.Y. Each of the below listed applications is hereby incorporated herein by reference in its entirety: [0002] U.S. Ser. No. 11/129,786 filed May 16, 2005 and entitled "A method for netlist path characteristics extraction" [0003] U.S. Ser. No. 11/129,785 filed May 16, 2005 and entitled "Negative Slack Recoverability Factor--A net weight to enhance timing closure behavior" TRADEMARKS [0004] IBM.RTM. is a registered trademark of International Business Machines Corporation, Armonk, N.Y., U.S.A. and other names used herein may be registered trademarks, trademarks or product names of International Business Machines Corporation or other companies. BACKGROUND OF THE INVENTION [0005] 1. Field of the Invention [0006] This invention relates to chip circuit design, and particularly a chip made using a tool for integrated circuit design, one which can analyze the data contained within an entire endpoint report, compute relationships between paths based on shared segments, and display this information graphically to the designer. [0007] 2. Description of Background [0008] When performing timing analysis of paths within chips there often are many hundreds or thousands of paths which fail to meet timing requirements. Many of those failing paths can be related in that a few common segments within them are causing timing failures, and all the rest of the connections within the paths are very close to or meet timing. Unfortunately, a tool does not exist which can find the commonality in failing paths. [0009] Commonly, these paths are reported to users in the form of an Endpoint Report. The Endpoint report is a text based file which contains detailed descriptions of timing test failures. Endpoint reports are very lengthy and verbose, requiring users to scroll horizontally and vertically. They do not group related paths nor identify the overlapping segments within them. There is a lot of information in an endpoint report; so much that often there is too much information for an engineer to comprehend. [0010] One known solution to the problem of having too much information can be found in the Critical Path Chart. This is a chart that graphically represents paths using multiple colors and bars of different length representing logic and wire delay. However, the critical path chart cannot find relationships between failing paths. The graphical representation can hint at the relationships, but the critical path chart does not definitively describe the commonality between them. [0011] A tool is needed which can condense many thousands of failing paths into a concise format which identifies repetition/commonality amongst those paths. Such a tool will save design engineers a lot of time in fixing timing problems by providing insight and priorities for fixing negative slack timing test failures. SUMMARY OF THE INVENTION [0012] The shortcomings of the prior art are overcome and additional advantages are provided by a chip made through the provision of the tool we call Genie which is a tool which can analyze the data contained within an entire endpoint report, compute relationships between paths based on shared segments, and display this information graphically to the designer. Specifically, Genie groups failing paths into Timing Islands. A timing island is a group of paths which contain at least one shared segment. The most frequently shared segment is sifted to the top of the priority list for each island, and is labeled as the Hub. Thinking of timing islands as a tree, the hub of the island would be the trunk. If you chop the tree down by the trunk, all of the branches, limbs and twigs will fall down too. This is analogous to fixing the timing failures in the hub, and the fix trickling out to each of the segments that dangle off the hub. [0013] Previously, using only endpoint reports or the critical path chart, users would not be able to easily identify the hub, and would spend days and weeks manually investigating individual paths. Users would often cull only the worst 500 or so failing paths and ignore the rest (perhaps thousands) because there was too much information to handle. [0014] Our system during setup allows the user to maker a choice between late mode and early mode for the Endpoint report and the tests they would like to run. [0015] System and computer program products corresponding to the above-summarized methods are also described and claimed herein. [0016] Additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention. For a better understanding of the invention with advantages and features, refer to the description and to the drawings. BRIEF DESCRIPTION OF THE DRAWINGS [0017] The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other objects, features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which: [0018] FIG. 1 illustrates one example of the application of the preferred embodiment where a timing island is a group of failing timing paths that contain at least one shared segment or hub. [0019] FIG. 2 illustrates an example of a preferred timing path flowchart for generating a timing island file which represents the islands. [0020] FIG. 3 illustrates a timing optimized VIM (VIM=VLSI Integrated Model) and a placement optimized VIM. Continue reading... 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