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Chip connectorRelated Patent Categories: Active Solid-state Devices (e.g., Transistors, Solid-state Diodes), Combined With Electrical Contact Or Lead, Chip Mounted On ChipChip connector description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070182020, Chip connector. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS REFERENCE TO RELATED APPLICATIONS [0001] This application is a Divisional Application of U.S. patent application Ser. No. 11/329,575, filed Jan. 10, 2006 which claims priority under 35 USC 119(e)(1) to U.S. Provisional Patent Application Ser. No. 60/690,759, filed Jun. 14, 2005, the entirety of both are incorporated herein by reference as if fully set forth herein. FIELD OF THE INVENTION [0002] The present invention relates to semiconductors and, more particularly, to electrical connections for such devices. BACKGROUND [0003] Making electrical contacts that extend all the way through an electronic chip (by creating electrically conductive vias) is difficult. Doing so with precision or controlled repeatability, let alone in volume is nearly impossible unless one or more of the following is the case: a) the vias are very shallow, i.e. significantly less than 100 microns in depth, b) the via width is large, or c) the vias are separated by large distances, i.e. many times the via width. The difficulty is compounded when the vias are close enough for signal cross-talk to occur, or if the chip through which the via passes has a charge, because the conductor in the via can not be allowed act as a short, nor can it carry a charge different from the charge of the pertinent portion of the chip. In addition, conventional processes, to the extent they exist, are unsuitable for use with formed integrated circuit (IC) chips (i.e. containing active semiconductor devices) and increase cost because those processes can damage the chips and thereby reduce the ultimate yield. Adding further to the above difficulties is the need to be concerned with capacitance and resistance problems when the material the via passes through has a charge or when the frequencies of the signals to be carried through the vias are very high, for example, in excess of about 0.3 GHz. [0004] Indeed, there are numerous problems that are extant in the semiconductor art including: use of large, non-scaleable packaging; assembly costs don't scale like semiconductors; chip cost is proportional to area, and the highest performance processes are the most expensive, but only fraction of chip area actually requires high-performance processes; current processes are limited in voltage and other technologies; chip designers are limited to one process and one material for design; large, high power pad drivers are needed for chip-to-chip (through package) connections; even small changes or correction of trivial design errors require fabrication of one or more new masks for a whole new chip; making whole new chips requires millions of dollars in mask costs alone; individual chips are difficult and complicated to test and combinations of chips are even more difficult to test prior to complete packaging. [0005] Accordingly, there is a significant need in the art for technology that can address one or more of the above problems. SUMMARY OF THE INVENTION [0006] We have developed a process that facilitates forming chip to chip electrical connections with vias that pass through a wafer, a preformed third-party chip, or a doped semiconductor substrate. Aspects described herein aid in the approach and represent improvements in the general field of joining of chips to each other. [0007] One aspect involves a method of electrically joining a first contact on a first wafer with a second contact on a second wafer, the first contact, a rigid material, and the second contact, a material that is malleable relative to the rigid material, such that when brought together the rigid material will penetrate the malleable material, the rigid and malleable materials both being electrically conductive involves bringing the rigid material into contact with the malleable material, applying a force to one of the first contact or the second contact so as to cause the rigid material to penetrate the malleable material, heating the rigid and malleable material so as to cause the malleable material to soften, and constraining the malleable material to within a pre-specified area. [0008] Another aspect involves forming a well on the second wafer in a shape that will bound the malleable material and perform the constraining. [0009] Yet another aspect involves applying the malleable material onto an IC pad of the second wafer, the IC pad being recessed relative to at least one of a cover glass of, or dielectric on, the second wafer that is located near the IC pad such that the malleable material in part rests on top of the IC pad and in part rests on top of the cover glass or dielectric or both so that an outer surface portion of the malleable material that is over the IC pad will be at a different elevation than another portion of the malleable material located over the cover glass or dielectric or both. [0010] Another aspect involves a connection formed between complementary contacts on two chips involves a first electrical contact on a first of the two chips, a second electrical contact on a second of the two chips, a bonding metal, physically and electrically joining the first and second electrical contacts, and a material peripherally bounding the bonding metal to prevent the bonding metal from bulging or creeping outward from the contacts in a lateral direction. [0011] The advantages and features described herein are a few of the many advantages and features available from representative embodiments and are presented only to assist in understanding the invention. It should be understood that they are not to be considered limitations on the invention as defined by the claims, or limitations on equivalents to the claims. For instance, some of these advantages are mutually contradictory, in that they cannot be simultaneously present in a single embodiment. Similarly, some advantages are applicable to one aspect of the invention, and inapplicable to others. Thus, this summary of features and advantages should not be considered dispositive in determining equivalence. Additional features and advantages of the invention will become apparent in the following description, from the drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS [0012] FIG. 1 is a simplified representation a side view of a portion of a chip containing multiple active electronic devices; [0013] FIG. 2 is a top view of the upper surface of the specified area of FIG. 1; [0014] FIG. 3 shows a simplified cutaway view of the portion of FIG. 1; [0015] FIG. 4 is a top view of the upper surface of the specified area of FIG. 1 following creation of the trench shown in side view in FIG. 3; [0016] FIG. 5 shows a simplified cutaway view of the portion of FIG. 1 as a result of continued processing; [0017] FIG. 6 is a top view of the upper surface of the specified area of FIG. 1 following the filling of the trench with electrically insulating material shown in side view in FIG. 5; [0018] FIG. 7 shows a simplified cutaway view of the portion of FIG. 1 as a result of continued processing; [0019] FIG. 8 is a top view of the upper surface of the specified area 124 of FIG. 1 following the creation of the via trench; Continue reading about Chip connector... Full patent description for Chip connector Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Chip connector patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Chip connector or other areas of interest. ### Previous Patent Application: Semiconductor devices and methods of manufacturing the same Next Patent Application: Integrated circuit package system including zero fillet resin Industry Class: Active solid-state devices (e.g., transistors, solid-state diodes) ### FreshPatents.com Support Thank you for viewing the Chip connector patent info. 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