| Chip burning system -> Monitor Keywords |
|
|
  Chip burning systemThe Patent Description & Claims data below is from USPTO Patent Application 20070145993. Brief Patent Description - Full Patent Description - Patent Application Claims
FIELD OF THE INVENTION [0001] The present invention relates to a system for burning chips, and more particularly to a system for burning chips on a motherboard. DESCRIPTION OF RELATED ART [0002] Generally, motherboards have a plurality of chips for different functions, such as BIOS (Basic Input Output System) chips, network card chips, and so on. [0003] Conventionally, the chips are burned before being attached to the motherboard. A typical chip-burning device includes a buffer, a micro processing unit, a burning unit, and a communication circuit. After a chip is burned by the chip-burning device, the chip is attached to the motherboard. However, pins of the chip are easily damaged during attachment to the motherboard due to misalignment of the pins to corresponding through holes of the motherboard. [0004] Another method of burning chips is to burn a chip after it is attached to the motherboard. A motherboard test machine that has a burning function is used to transfer the data to the chip via a serial port and burn the data into the chip. However, the machine can burn only one chip at a time, which is time consuming and expensive. [0005] What is needed, therefore, is a more efficient system for burning chips of a motherboard. SUMMARY OF THE INVENTION [0006] A chip burning system includes a burning device with a plurality of burning files stored therein, a transforming circuit for connecting to chips via serial interfaces, a control unit interconnecting the burning device and the transforming circuit via parallel interfaces, and two chips for burning. The transforming circuit includes a parallel-to-serial conversion module. The control unit includes a terminal configured to output a chip choosing signal to the transforming circuit for choosing one chip from the two chips. The burning device transmits a parallel type burning file to the transforming circuit via the control unit. The transforming circuit transforms the burning file into serial type with the parallel-to-serial conversion module, and the transformed burning file is burned into the chosen chip. [0007] Other advantages and novel features will be drawn from the following detailed description of a preferred embodiment with attached drawings, in which: BRIEF DESCRIPTION OF THE DRAWINGS [0008] FIG. 1 is a block diagram of an exemplary chip burning system in accordance with a preferred embodiment of the present invention, which includes a burning device, a control unit, and a transforming circuit; and [0009] FIG. 2 is a schematic diagram of the transforming circuit of FIG. 1. DETAILED DESCRIPTION OF THE INVENTION [0010] Referring to FIG. 1, a chip burning system in accordance with a preferred embodiment of the present invention includes a burning device 10, a control unit 20 and a transforming circuit 30 attached on the burning device 10. The chip burning system is used to burn a first chip 40 and a second chip 50 of a motherboard (not shown). [0011] The burning device 10 stores a plurality of burning files corresponding to the first chip 40 and the second chip 50 respectively. The burning device 10 is connected to the control unit 20 via a parallel interface. [0012] The control unit 20 is used to control the burning process. The control unit 20 includes a parallel output port 22, a parallel input port 24, and a plurality of control terminals 25, 26, 27, and 28. The control terminal 25 outputs a transmitting data signal to control the data transmission between the control unit 20 and the transforming circuit 30. The control terminal 26 outputs a read/write control signal to control reading or writing data from or to the first and second chips 40 and 50. The control terminal 27 outputs a chip-activated signal for activating a chip. The terminal 28 outputs a chip choosing signal for choosing a chip. [0013] The transforming circuit 30 includes a parallel input port 32 connected to the parallel output port 22, and a parallel output port 34 connected to the parallel input port 24. The transforming circuit 30 has two series of terminals connected to the first chip 40 and the second chip 50 respectively. One series of terminals includes terminals 351, 352, 353, and 354, and the other series of terminals includes terminals 361, 362, 363, and 364. [0014] The terminal 351 outputs a clock signal to the first chip 40. The terminals 352, 354 are serial interfaces. The terminal 352 is series connected to the first chip 40 for writing data to the first chip 40. The terminal 353 outputs the chip-activated signal to the first chip 40. The terminal 354 is series connected to the first chip 40 for reading data from the first chip 40. [0015] The terminal 361 outputs a clock signal to the second chip 50. The terminal 362 is series connected to the second chip 50 for writing data to the second chip 50. The terminal 363 outputs the chip-activated signal to the second chip 50. The terminal 364 is series connected to the second chip 50 for reading data from the second chip 50. [0016] Referring to FIG. 2, the details of the transforming circuit 30 are shown. The transforming circuit 30 includes a parallel-to-serial conversion module 301, a serial-to-parallel conversion module 302, a plurality of buffers 303a to 303k, two phase inverters 304a, 304b, an oscillating crystal 305, and a frequency demultiplier 306. Each buffer includes an input terminal, an output terminal, and a control terminal. [0017] An input terminal of the parallel-to-serial conversion module 301 is connected to the parallel input port 32. An output terminal of the parallel-to-serial conversion 301 is connected to an input terminal of the buffer 303b for transmitting data to the chips 40 and 50. [0018] An input terminal of the serial-to-parallel conversion module 302 is connected to an output terminal of the buffer 303c. An output terminal of the serial-to-parallel conversion 302 is connected to the parallel output terminal 34. [0019] An input terminal of the buffer 303a is connected to the terminal 26. A control terminal of the buffer 303a is connected to the terminal 25. When the terminal 25 is enabled at a high level, the buffer 303a conducts to transmit the read/write control signal from the terminal 26 to an output terminal of the buffer 303a. The output terminal of the buffer 303a is connected to the control terminal of the buffer 303b, and is connected to the control terminal of the buffer 303c via the phase inverter 304a. Continue reading... Full patent description for Chip burning system Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Chip burning system patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Chip burning system or other areas of interest. ### Previous Patent Application: Semiconductor device testing system and semiconductor device testing method Next Patent Application: Socket and test apparatus Industry Class: Electricity: measuring and testing ### FreshPatents.com Support Thank you for viewing the Chip burning system patent info. IP-related news and info Results in 0.2086 seconds Other interesting Feshpatents.com categories: Tyco , Unilever , Warner-lambert , 3m |
||
