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Chih-Chao Yang patents

Recent bibliographic sampling of Chih-Chao Yang patents listed/published in the public domain by the USPTO (USPTO Patent Application #,Title):



03/12/15 - 20150069625 - Ultra-thin metal wires formed through selective deposition
The embodiments of the present invention relate generally to the fabrication of integrated circuits, and more particularly to a structure and method for fabricating a pair of ultra-thin metal wires in an opening using a selective deposition process....
Inventors: Juntao Li, Chih-chao Yang, Yunpeng Yin (International Business Machines Corporation)

03/05/15 - 20150061040 - Self-aligned dielectric isolation for finfet devices
Embodiments of the present invention provide a method of forming semiconductor structure. The method includes forming a set of device features on top of a substrate; forming a first dielectric layer directly on top of the set of device features and on top of the substrate, thereby creating a height...
Inventors: Marc Adam Bergendahl, Kangguo Cheng, David Vaclav Horak, Ali Khakifirooz, Shom Ponoth, Theodorus Eduardus Standaert, Chih-chao Yang, Charles William Koburger, Iii, Xiuyu Cai, Ruilong Xie (Globalfoundries, Inc.)

02/05/15 - 20150035157 - Spacer for enhancing via pattern overlay tolerence
After formation of line openings in a hard mask layer, hard mask level spacers are formed on sidewalls of the hard mask layer. A photoresist is applied and patterned to form a via pattern including a via opening. The overlay tolerance for printing the via pattern is increased by the...
Inventors: Steven J. Holmes, David V. Horak, Charles W. Koburger, Iii, Shom Ponoth, Chih-chao Yang (International Business Machines Corporation)

02/05/15 - 20150035155 - Dual damascene structure with liner
A dual damascene structure with an embedded liner and methods of manufacture are disclosed. The method includes forming a dual damascene structure in a substrate. The method further includes reflowing a seed layer such that material of the seed layer flows into a via of the dual damascene structure. The...
Inventors: Baozhen Li, Chih-chao Yang (International Business Machines Corporation)

02/05/15 - 20150035154 - Profile control in interconnect structures
The profile of a via can be controlled by forming a profile control liner within each via opening that is formed into a dielectric material prior to forming a line opening within the dielectric material. The presence of the profile control liner within each via opening during the formation of...
Inventors: Shyng-tsong Chen, Samuel S. Choi, Steven J. Holmes, David V. Horak, Charles W. Koburger, Iii, Wai-kin Li, Christopher J. Penny, Shom Ponoth, Chih-chao Yang, Yunpeng Yin (International Business Machines Corporation)

01/08/15 - 20150008527 - Integrated circuit structure having selectively formed metal cap
An integrated circuit structure with a selectively formed and at least partially oxidized metal cap over a gate. In one embodiment, an integrated circuit structure has: a substrate; a metal gate located over the substrate; at least one liner layer over the substrate and substantially surrounding the metal gate; and...
Inventors: Chih-chao Yang, David V. Horak, Charles W. Koburger, Shom Ponoth (International Business Machines Corporation)

12/11/14 - 20140363941 - Replacement gate electrode with a self-aligned dielectric spacer
A dielectric disposable gate structure can be formed across a semiconductor material portion, and active semiconductor regions are formed within the semiconductor material portion. Raised active semiconductor regions are grown over the active semiconductor regions while the dielectric disposable gate structure limits the extent of the raised active semiconductor regions....
Inventors: Shom Ponoth, Marc A. Bergendahl, Steven J. Holmes, David V. Horak, Charles W. Koburger, Iii, Chih-chao Yang

11/20/14 - 20140342549 - Dual damascene dual alignment interconnect scheme
A stack of a first metal line and a first dielectric cap material portion is formed within a line trench of first dielectric material layer. A second dielectric material layer is formed thereafter. A line trench extending between the top surface and the bottom surface of the second dielectric material...
Inventors: Steven J. Holmes, David V. Horak, Charles W. Koburger, Iii, Shom Ponoth, Chih-chao Yang

11/13/14 - 20140332964 - Interconnect structures containing nitrided metallic residues
A metal cap is formed on an exposed upper surface of a conductive structure that is embedded within an interconnect dielectric material. During the formation of the metal cap, metallic residues simultaneously form on an exposed upper surface of the interconnect dielectric material. A thermal nitridization process or plasma nitridation...
Inventors: Chih-chao Yang, Stephan A. Cohen (International Business Machines Corporation)

11/13/14 - 20140332960 - Interconnect structures containing nitrided metallic residues
A metal cap is formed on an exposed upper surface of a conductive structure that is embedded within an interconnect dielectric material. During the formation of the metal cap, metallic residues simultaneously form on an exposed upper surface of the interconnect dielectric material. A thermal nitridization process or plasma nitridation...
Inventors: Chih-chao Yang, Stephan A. Cohen (International Business Machines Corporation)

10/30/14 - 20140319650 - Programmable electrical fuse
An method and structure of forming an electronic fuse. The method including forming a first metal line and a second metal line in a first interconnect level, wherein the first metal line is electrically insulated form the second metal line, and forming a via in a second interconnect level above...
Inventors: Jason Coyner, Baozhen Li, Keith Kwong Hon Wong, Chih-chao Yang (International Business Machines Corporation)

10/02/14 - 20140291760 - Fet semiconductor device with low resistance and enhanced metal fill
In a method of fabricating a FET semiconductor device, a FET structure with a gate channel and dummy gate is formed on a layer of substrate. The gate channel includes one or more FINs, and spacer layers that line the sides of the gate channel and abut the layer of...
Inventors: Kangguo Cheng, Junli Wang, Keith Kwong Hon Wong, Chih-chao Yang

09/18/14 - 20140264878 - Copper interconnect structures and methods of making same
A structure and method of making the structure. The structure includes a dielectric layer on a substrate; a first wire formed in a first trench in the dielectric layer, a first liner on sidewalls and a bottom of the first trench and a first copper layer filling all remaining space...
Inventors: Chih-chao Yang, Marc A. Bergendahl, David V. Horak, Baozhen Li, Shom Ponoth (International Business Machines Corporation)

09/18/14 - 20140264490 - Replacement gate electrode with a self-aligned dielectric spacer
A dielectric disposable gate structure can be formed across a semiconductor material portion, and active semiconductor regions are formed within the semiconductor material portion. Raised active semiconductor regions are grown over the active semiconductor regions while the dielectric disposable gate structure limits the extent of the raised active semiconductor regions....
Inventors: Shom Ponoth, Marc A. Bergendahl, Steven J. Holmes, David V. Horak, Charles W. Koburger, Iii, Chih-chao Yang (International Business Machines Corporation)

08/28/14 - 20140239439 - Electrical fuses and methods of making electrical fuses
A fuse, a method of making the fuse and a circuit containing the fuse. The fuse includes an electrically conductive and conformal liner on sidewalls and the bottom of a trench; a copper layer on the conformal liner, a first thickness of the copper layer over the bottom of the...
Inventors: Nicholas R. Hogle, Baozhen Li, Keith Kwong Hon Wong, Chih-chao Yang (International Business Machines Corporation)

08/21/14 - 20140231918 - Finfets and fin isolation structures
FinFETs and fin isolation structures and methods of manufacturing the same are disclosed. The method includes patterning a bulk substrate to form a plurality of fin structures of a first dimension and of a second dimension. The method includes forming oxide material in spaces between the plurality of fin structures...
Inventors: Marc A. Bergendahl, David V. Horak, Charles W. Koburger, Iii, Shom Ponoth, Chih-chao Yang (International Business Machines Corporation)

08/07/14 - 20140220777 - Processing system for combined metal deposition and reflow anneal for forming interconnect structures
An interconnect conductive metal used in forming an interconnect structure can be formed using a method in which deposition of a metal liner and a reflow anneal are performed in a same multi-chambered processing system without exposing the structure to air between the steps of deposition and reflow annealing. In...
Inventors: Chih-chao Yang, Stephan A. Cohen, Joseph F. Maniscalco (International Business Machines Corporation)

08/07/14 - 20140216342 - Processing system for combined metal deposition and reflow anneal for forming interconnect structures
An interconnect conductive metal used in forming an interconnect structure can be formed using a method in which deposition of a metal liner and a reflow anneal are performed in a same multi-chambered processing system without exposing the structure to air between the steps of deposition and reflow annealing. In...
Inventors: Chih-chao Yang, Stephan A. Cohen, Joseph F. Maniscalco (International Business Machines Corporation)

07/31/14 - 20140210041 - Electronic fuse having an insulation layer
An electronic fuse structure including etching a dual damascene feature in a dielectric layer, the dual damascene feature including a first via opening, a second via opening, and a trench opening, forming a seed layer within the dual damascene feature, the seed layer including a conductive material, and heating the...
Inventors: Chad M. Burke, Baozhen Li, Keith Kwong Hon Wong, Chih-chao Yang (International Business Machines Corporation)

07/24/14 - 20140206190 - Silicide formation in high-aspect ratio structures
Embodiments of the present invention include methods of forming a silicide layer on a semiconductor substrate. In an exemplary embodiment, a metal layer may first be deposited above a semiconductor substrate using a chemical vapor deposition process with a metal amidinate precursor and then the semiconductor substrate may be annealed,...
Inventors: Baozhen Li, Yun Y. Wang, Keith Kwong Hon Wong, Chih-chao Yang (International Business Machines Corporation)

07/24/14 - 20140203453 - Air-dielectric for subtractive etch line and via metallization
A method and structure is disclosed whereby multiple interconnect layers having effective air gaps positioned in regions most susceptible to capacitive coupling can be formed. The method includes providing a layer of conductive features, the layer including at least two line members disposed on a substrate and spaced from one...
Inventors: David V. Horak, Elbert Huang, Charles W. Koburger, Iii, Shom Ponoth, Chih-chao Yang (International Business Machines Corporation)

07/10/14 - 20140191323 - Method of forming finfet of variable channel width
Embodiments of present invention provide a method of forming a first and a second group of fins on a substrate; covering a top first portion of the first and second groups of fins with a first dielectric material; covering a bottom second portion of the first and second groups of...
Inventors: Marc Adam Bergendahl, David Vaclav Horak, Shom Ponoth, Chih-chao Yang, Charles William Koburger, Iii (International Business Machines Corporation)

07/10/14 - 20140191296 - Self-aligned dielectric isolation for finfet devices
Embodiments of the present invention provide a method of forming semiconductor structure. The method includes forming a set of device features on top of a substrate; forming a first dielectric layer directly on top of the set of device features and on top of the substrate, thereby creating a height...
Inventors: Marc Adam Bergendahl, Kangguo Cheng, David Vaclav Horak, Ali Khakifirooz, Shom Ponoth, Theodorus Eduardus Standaert, Chih-chao Yang, Charles William Koburger, Iii, Xiuyu Cai, Ruilong Xie (International Business Machines Corporation)

07/10/14 - 20140190935 - Dual mandrel sidewall image transfer processes
A combination of two lithographically patterned mandrels can be employed in conjunction with sidewall spacers to provide two spacers. The two spacers may intersect each other and/or contact sidewall surfaces of each other to provide a thickness that is a sum of the thicknesses of the two spacers. Further, the...
Inventors: David V. Horak, Charles W. Koburger, Iii, Shom Ponoth, Chih-chao Yang (International Business Machines Corporation)

07/03/14 - 20140183739 - Dual damascene structure with liner
A dual damascene structure with an embedded liner and methods of manufacture are disclosed. The method includes forming a dual damascene structure in a substrate. The method further includes reflowing a seed layer such that material of the seed layer flows into a via of the dual damascene structure. The...
Inventors: Baozhen Li, Chih-chao Yang (International Business Machines Corporation)

06/12/14 - 20140162450 - Interconnect structure with an electromigration and stress migration enhancement liner
An electromigration and stress migration enhancement liner is provided for use in an interconnect structure. The liner includes a metal that has a thickness at a bottom of the at least one via opening and on an exposed portion of an underlying conductive feature that is greater than a remaining...
Inventors: Chih-chao Yang, Baozhen Li (International Business Machines Corporation)

06/05/14 - 20140154846 - Semiconductor device with raised source/drain and replacement metal gate
In a method of fabricating a semiconductor device, a silicon-on-insulator (SOI) substrate is provided. This SOI substrate comprises a buried oxide layer and an ETSOI layer between the buried oxide layer and a surface of the SOI substrate. A dummy gate is formed on the ETSOI. At least two raised...
Inventors: Kangguo Cheng, Junli Wang, Keith Kwong Hon Wong, Chih-chao Yang (International Business Machines Corporation)

06/05/14 - 20140151097 - Method and structure to improve the conductivity of narrow copper filled vias
Techniques for improving the conductivity of copper (Cu)-filled vias are provided. In one aspect, a method of fabricating a Cu-filled via is provided. The method includes the following steps. A via is etched in a dielectric. The via is lined with a diffusion barrier. A thin ruthenium (Ru) layer is...
Inventors: Fenton R. Mcfeely, Chih-chao Yang (International Business Machines Corporation)

05/08/14 - 20140124933 - Copper interconnect structures and methods of making same
A structure and method of making the structure. The structure includes a dielectric layer on a substrate; a first wire formed in a first trench in the dielectric layer, a first liner on sidewalls and a bottom of the first trench and a first copper layer filling all remaining space...
Inventors: Chih-chao Yang, Marc A. Bergendahl, David V. Horak, Baozhen Li, Shom Ponoth (International Business Machines Corporation)

05/01/14 - 20140120709 - Insulative cap for borderless self-aligning contact in semiconductor device
A method comprises: forming a semiconductor device on a base substrate, the semiconductor device having a core metal positioned proximate a source and a drain in the base substrate, a work function metal on a portion of the core metal, and a dielectric layer on a portion of the work...
Inventors: Kangguo Cheng, Junli Wang, Keith Kwong Hon Wong, Chih-chao Yang (International Business Machines Corporation)

05/01/14 - 20140117423 - Insulative cap for borderless self-aligning contact in semiconductor device
An apparatus comprises: a semiconductor device on a base substrate, the semiconductor device having a core metal positioned proximate a source and a drain in the base substrate; a work function metal on a portion of the core metal; a dielectric liner on a portion of the work function metal;...
Inventors: Kangguo Cheng, Junli Wang, Keith Kwong Hon Wong, Chih-chao Yang (International Business Machines Corporation)

04/24/14 - 20140110817 - Sub-lithographic semiconductor structures with non-constant pitch
Fin structures and methods of manufacturing fin structures using a dual-material sidewall image transfer mask to enable patterning of sub-lithographic features is disclosed. The method of forming a plurality of fins includes forming a first set of fins having a first pitch. The method further includes forming an adjacent fin...
Inventors: Marc A. Bergendahl, David V. Horak, Charles W. Koburger, Iii, Shom Ponoth, Chih-chao Yang (International Business Machines Corporation)

04/10/14 - 20140099792 - Single fin cut employing angled processing methods
Fin-defining spacers are formed on an array of mandrel structure. Mask material portions can be directionally deposited on fin-defining spacers located on one side of each mandrel structure, while not deposited on the other side. A photoresist layer is subsequently applied and patterned to form an opening, of which the...
Inventors: Marc A. Bergendahl, David V. Horak, Charles W. Koburger, Iii, Shom Ponoth, Chih-chao Yang (International Business Machines Corporation)

03/06/14 - 20140068541 - Interconnect structures and methods for back end of the line integration
A method of forming a semiconductor structure includes forming a sacrificial conductive material layer. The method also includes forming a trench in the sacrificial conductive material layer. The method further includes forming a conductive feature in the trench. The method additionally includes removing the sacrificial conductive material layer selective to...
Inventors: David V. Horak, Charles W. Koburger, Iii, Shom Ponoth, Chih-chao Yang (International Business Machines Corporation)

03/06/14 - 20140065813 - Size-filtered multimetal structures
A size-filtered metal interconnect structure allows formation of metal structures having different compositions. Trenches having different widths are formed in a dielectric material layer. A blocking material layer is conformally deposited to completely fill trenches having a width less than a threshold width. An isotropic etch is performed to remove...
Inventors: David V. Horak, Charles W. Koburger, Iii, Shom Ponoth, Chih-chao Yang (International Business Machines Corporation)

03/06/14 - 20140061930 - Overlay-tolerant via mask and reactive ion etch (rie) technique
A method is provided that includes first etching a substrate according to a first mask. The first etching forms a first etch feature in the substrate to a first depth. The first etching also forms a sliver opening in the substrate. The sliver opening may then be filled with a...
Inventors: Steven J. Holmes, David V. Horak, Charles W. Koburger, Iii, Shom Ponoth, Chih-chao Yang (International Business Machines Corporation)

02/20/14 - 20140048927 - Method to improve fine cu line reliability in an integrated circuit device
Structure and methods for forming a semiconductor structure. The semiconductor structure includes a plurality of layers comprising at least one copper interconnect layer. The copper interconnect layer provides an electrical conduit between one of physically adjacent layers in the semiconductor structure and an integrated circuit in the semiconductor structure and...
Inventors: Chad M. Burke, Baozhen Li, Keith Kwong Hon Wong, Chih-chao Yang (International Business Machines Corporation)

02/20/14 - 20140048905 - Low cost anti-fuse structure
An anti-fuse structure is provided in which an anti-fuse material liner is embedded within one of the openings provided within an interconnect dielectric material. The anti-fuse material liner is located between a first conductive metal and a second conductive metal which are also present within the opening. A diffusion barrier...
Inventors: Chih-chao Yang, Stephen M. Gates (International Business Machines Corporation)

02/06/14 - 20140035142 - Profile control in interconnect structures
The profile of a via can be controlled by forming a profile control liner within each via opening that is formed into a dielectric material prior to forming a line opening within the dielectric material. The presence of the profile control liner within each via opening during the formation of...
Inventors: Chih-chao Yang, Shyng-tsong Chen, Samuel S. Choi, Steven J. Holmes, David V. Horak, Charles W. Koburger, Iii, Wai-kin Li, Christopher J. Penny, Shom Ponoth, Yunpeng Yin (International Business Machines Corporation)

01/30/14 - 20140027865 - Mosfet gate and source/drain contact metallization
A MOSFET is described incorporating a common metal process to make contact to the source, drain and the metal gate respectively which may be formed concurrently with the same metal or metals....


01/23/14 - 20140024210 - Low cost anti-fuse structure and method to make same
An anti-fuse structure is provided in which an anti-fuse material liner is embedded within one of the openings provided within an interconnect dielectric material. The anti-fuse material liner is located between a first conductive metal and a second conductive metal which are also present within the opening. A diffusion barrier...


01/23/14 - 20140021581 - Low cost anti-fuse structure
An anti-fuse structure is provided in which an anti-fuse material liner is embedded within one of the openings provided within an interconnect dielectric material. The anti-fuse material liner is located between a first conductive metal and a second conductive metal which are also present within the opening. A diffusion barrier...


01/09/14 - 20140008764 - High-nitrogen content metal resistor and method of forming same
A thin film metal resistor is provided that includes an in-situ formed metal nitride layer formed in a lower region of a metal nitride layer. The in-situ formed metal nitride layer, together with the overlying metal nitride layer, from a thin film metal resistor which has a nitrogen content that...


12/19/13 - 20130334580 - Replacement metal gate processing with reduced interlevel dielectric layer etch rate
A semiconductor structure includes an interlevel dielectric (ILD) layer disposed over a semiconductor substrate and a transistor gate structure formed on the substrate; and a shallow gas cluster ion beam (GCIB) layer infused in a top portion of the ILD layer; wherein the GCIB layer has a slower etch rate...


12/12/13 - 20130328208 - Dual damascene dual alignment interconnect scheme
A stack of a first metal line and a first dielectric cap material portion is formed within a line trench of first dielectric material layer. A second dielectric material layer is formed thereafter. A line trench extending between the top surface and the bottom surface of the second dielectric material...


12/12/13 - 20130328167 - Self-aligned metal-insulator-metal (mim) capacitor
A metal-insulator-metal (MIM) capacitor structure integrated within a back-end-of-the-line (BEOL) structure is provided. The MIM capacitor structure includes a lower electrode, i.e., a first conductive material, embedded within a dielectric material of the BEOL structure, a dielectric material liner having a dielectric constant of equal to, or greater than, silicon...


12/05/13 - 20130320546 - Dual-metal self-aligned wires and vias
Disclosed is a semiconductor structure which includes a semiconductor substrate and a wiring layer on the semiconductor substrate. The wiring layer includes a plurality of fin-like structures comprising a first metal; a first layer of a second metal on each of the plurality of fin-like structures wherein the first metal...


12/05/13 - 20130320545 - Hybrid copper interconnect structure and method of fabricating same
A hybrid interconnect structure containing copper regions that have different impurities levels within a same opening is provided. In one embodiment, the interconnect structure includes a patterned dielectric material having at least one opening located therein. A dual material liner is located at least on sidewalls of the patterned dielectric...


12/05/13 - 20130320414 - Borderless contacts for metal gates through selective cap deposition
A semiconductor device including a gate structure present on a channel portion of a substrate, in which the gate structure includes at least one high-k gate dielectric layer and at least one metal gate conductor. A source region and a drain region is present on opposing sides of the channel...


12/05/13 - 20130320411 - Borderless contacts for metal gates through selective cap deposition
A semiconductor device including a gate structure present on a channel portion of a substrate, in which the gate structure includes at least one high-k gate dielectric layer and at least one metal gate conductor. A source region and a drain region is present on opposing sides of the channel...


11/28/13 - 20130313717 - Spacer for enhancing via pattern overlay tolerence
After formation of line openings in a hard mask layer, hard mask level spacers are formed on sidewalls of the hard mask layer. A photoresist is applied and patterned to form a via pattern including a via opening. The overlay tolerance for printing the via pattern is increased by the...


11/21/13 - 20130309857 - Mask free protection of work function material portions in wide replacement gate electrodes
In a replacement gate scheme, after formation of a gate dielectric layer, a work function material layer completely fills a narrow gate trench, while not filling a wide gate trench. A dielectric material layer is deposited and planarized over the work function material layer, and is subsequently recessed to form...


11/21/13 - 20130307086 - Mask free protection of work function material portions in wide replacement gate electrodes
In a replacement gate scheme, after formation of a gate dielectric layer, a work function material layer completely fills a narrow gate trench, while not filling a wide gate trench. A dielectric material layer is deposited and planarized over the work function material layer, and is subsequently recessed to form...


10/03/13 - 20130260530 - Modularized three-dimensional capacitor array
A modularized capacitor array includes a plurality of capacitor modules. Each capacitor module includes a capacitor and a switching device that is configured to electrically disconnect the capacitor. The switching device includes a sensing unit configured to detect the level of leakage of the capacitor so that the switching device...


09/26/13 - 20130252419 - Metal alloy cap integration
A metal interconnect structure, which includes metal alloy capping layers, and a method of manufacturing the same. The originally deposited alloy capping layer element within the interconnect features will diffuse into and segregate onto top surface of the metal interconnect. The metal alloy capping material is deposited on a reflowed...


09/26/13 - 20130252415 - Structure and process for metallization in high aspect ratio features
A high aspect ratio metallization structure is provided in which a noble metal-containing material is present at least within a lower portion of a contact opening located in a dielectric material and is in direct contact with a metal semiconductor alloy located on an upper surface of a material stack...


09/05/13 - 20130230983 - Hybrid interconnect structure for performance improvement and reliability enhancement
A method of forming a hybrid interconnect structure including dielectric spacers is provided. The method includes forming at least one opening in a dielectric material utilizing a patterned hard mask located on a surface of the dielectric material as a mask, wherein an undercut is present beneath said patterned hard...


09/05/13 - 20130228925 - Hybrid interconnect structure for performance improvement and reliability enhancement
A hybrid interconnect structure is provided that includes a dielectric material having a conductive material embedded within at least one opening in the dielectric material, wherein the conductive material is laterally spaced apart from the dielectric material by a diffusion barrier, a dense dielectric spacer and, optionally, an air gap....


08/29/13 - 20130221529 - Hybrid interconnect structure for performance improvement and reliability enhancement
A hybrid interconnect structure (of the single or dual damascene type) is provided in which a dense (i.e., non-porous) dielectric spacer is present on the sidewalls of a dielectric material. More specifically, the structure includes a dielectric material having a conductive material embedded within at least one opening in the...


08/29/13 - 20130221527 - Metallic capped interconnect structure with high electromigration resistance and low resistivity
An interconnect structure including a metallic cap that covers 80 to 99% of the entire surface of an underlying conductive metal feature is provided utilizing a metal reflow process. Laterally extending portions of the conductive metal feature are located on vertical edges of the metallic cap, and each of the...


08/15/13 - 20130207270 - Dual-metal self-aligned wires and vias
Method of forming a semiconductor structure which includes forming first conductive spacers on a semiconductor substrate; forming second conductive spacers with respect to the first conductive spacers, at least one of the second conductive spacers adjacent to and in contact with each of the first conductive spacers to form combined...


08/01/13 - 20130193579 - Structure for nano-scale metallization and method for fabricating same
A method for forming structure aligned with features underlying an opaque layer is provided for an interconnect structure, such as an integrated circuit. In one embodiment, the method includes forming an opaque layer over a first layer, the first layer having a surface topography that maps to at least one...


07/18/13 - 20130181261 - Borderless contact structure
A borderless contact structure or partially borderless contact structure and methods of manufacture are disclosed. The method includes forming a gate structure and a space within the gate structure, defined by spacers. The method further includes blanket depositing a sealing material in the space, over the gate structure and on...


07/04/13 - 20130168863 - Enhanced diffusion barrier for interconnect structures
Alternative methods of fabricating an interconnect structure in which an enhanced diffusion barrier including an in-situ formed metal nitride liner formed between an interconnect dielectric material and an overlying metal diffusion barrier liner are provided. In one embodiment, at least one opening is formed into an interconnect dielectric material. A...


07/04/13 - 20130168807 - Interconnect structure containing various capping materials for electrical fuse and other related applications, and design structure thereof
A structure and design structure is provided for interconnect structures containing various capping materials for electrical fuses and other related applications. The structure includes a first interconnect structure having a first interfacial structure and a second interconnect structure adjacent to the first structure. The second interconnect structure has second interfacial...


07/04/13 - 20130168806 - Electrical fuse structure and method of fabricating same
A high programming efficiency electrical fuse is provided utilizing a dual damascene structure located atop a metal layer. The dual damascene structure includes a patterned dielectric material having a line opening located above and connected to an underlying via opening. The via opening is located atop and is connected to...


07/04/13 - 20130168749 - Borderless contact structure employing dual etch stop layers
Each gate structure formed on the substrate includes a gate dielectric, a gate conductor, a first etch stop layer, and a gate cap dielectric. A second etch stop layer is formed over the gate structures, gate spacers, and source and drain regions. A first contact-level dielectric layer and a second...


06/27/13 - 20130164905 - 3d via capacitor with a floating conductive plate for improved reliability
The present invention provides a 3D via capacitor and a method for forming the same. The capacitor includes an insulating layer on a substrate. The insulating layer has a via having sidewalls and a bottom. A first electrode overlies the sidewalls and at least a portion of the bottom of...


06/27/13 - 20130161791 - 3d via capacitor with a floating conductive plate for improved reliability
The present invention provides a 3D via capacitor and a method for forming the same. The capacitor includes an insulating layer on a substrate. The insulating layer has a via having sidewalls and a bottom. A first electrode overlies the sidewalls and at least a portion of the bottom of...


06/27/13 - 20130161697 - Replacement gate mosfet with raised source and drain
A disposable dielectric spacer is formed on sidewalls of a disposable material stack. Raised source/drain regions are formed on planar source/drain regions by selective epitaxy. The disposable dielectric spacer is removed to expose portions of a semiconductor layer between the disposable material stack and the source/drain regions including the raised...


06/13/13 - 20130149859 - Tungsten metallization: structure and fabrication of same
A local interconnect structure is provided in which a tungsten region, i.e., tungsten stud, that is formed within a middle-of-the-line (MOL) dielectric material is not damaged and/or contaminated during a multiple interconnect patterning process. This is achieved in the present disclosure by forming a self-aligned tungsten nitride passivation layer within...


05/30/13 - 20130134590 - Formation of air gap with protection of metal lines
A microelectronic substrate which includes a dielectric layer overlying a semiconductor region of a substrate, the dielectric layer having an exposed top surface; a plurality of metal lines of a first metal disposed within the dielectric layer, each metal line having edges and a surface exposed at the top surface...


05/23/13 - 20130126817 - E-fuses containing at least one underlying tungsten contact for programming
Semiconductor structures are provided containing an electronic fuse (E-fuse) that includes a fuse element and at least one underlying tungsten contact that is used for programming the fuse element. In some embodiments, a pair of neighboring tungsten contacts is used for programming the fuse element. In another embodiment, an overlying...


05/09/13 - 20130115767 - Metal alloy cap integration
A metal interconnect structure, which includes metal alloy capping layers, and a method of manufacturing the same. The originally deposited alloy capping layer element within the interconnect features will diffuse into and segregate onto top surface of the metal interconnect. The metal alloy capping material is deposited on a reflowed...


05/09/13 - 20130113101 - Use of gas cluster ion beam to reduce metal void formation in interconnect structures
A gas cluster ion beam process is used to reduce and/or even eliminate metal void formation in an interconnect structure. In one embodiment, gas cluster ion beam etching forms a chamfer opening in an interconnect dielectric material. In another embodiment, gas cluster ion beam etching reduces the overhang profile of...


04/18/13 - 20130093089 - Interconnect structure with an electromigration and stress migration enhancement liner
An electromigration and stress migration enhancement liner is provided for use in an interconnect structure. The liner includes a metal that has a thickness at a bottom of the at least one via opening and on an exposed portion of an underlying conductive feature that is greater than a remaining...


03/21/13 - 20130071998 - Electrical fuse with metal line migration
An electrical fuse device is disclosed. A circuit apparatus can include the fuse device, a first circuit element and a second circuit element. The fuse includes a first contact that has a first electromigration resistance, a second contact that has a second electromigration resistance and a metal line, which is...


03/21/13 - 20130069161 - Integrated circuit structure having selectively formed metal cap
Methods of forming an integrated circuit structure utilizing a selectively formed and at least partially oxidized metal cap over a gate, and associated structures. In one embodiment, a method includes providing a precursor structure including a transistor having a metal gate; forming an etch stop layer over an exposed portion...


02/21/13 - 20130043591 - Tungsten metallization: structure and fabrication of same
A local interconnect structure is provided in which a tungsten region, i.e., tungsten stud, that is formed within a middle-of-the-line (MOL) dielectric material is not damaged and/or contaminated during a multiple interconnect patterning process. This is achieved in the present disclosure by forming a self-aligned tungsten nitride passivation layer within...


02/21/13 - 20130043556 - Size-filtered multimetal structures
A size-filtered metal interconnect structure allows formation of metal structures having different compositions. Trenches having different widths are formed in a dielectric material layer. A blocking material layer is conformally deposited to completely fill trenches having a width less than a threshold width. An isotropic etch is performed to remove...


02/14/13 - 20130037865 - Semiconductor structure having a wetting layer
A semiconductor structure which includes a semiconductor substrate and a metal gate structure formed in a trench or via on the semiconductor substrate. The metal gate structure includes a gate dielectric; a wetting layer selected from the group consisting of cobalt and nickel on the gate dielectric lining the trench...


01/31/13 - 20130026635 - Hybrid copper interconnect structure and method of fabricating same
A hybrid interconnect structure containing copper regions that have different impurities levels within a same opening is provided. In one embodiment, the interconnect structure includes a patterned dielectric material having at least one opening located therein. A dual material liner is located at least on sidewalls of the patterned dielectric...


12/27/12 - 20120329275 - Borderless interconnect line structure self-aligned to upper and lower level contact vias
A metal layer is deposited on a planar surface on which top surfaces of underlying metal vias are exposed. The metal layer is patterned to form at least one metal block, which has a horizontal cross-sectional area of a metal line to be formed and at least one overlying metal...


12/27/12 - 20120329271 - Discontinuous/non-uniform metal cap structure and process for interconnect integration
A method of fabricating an interconnect structure is provided which includes providing a dielectric material having a dielectric constant of about 3.0 or less and at least one conductive material embedded therein, the at least one conductive material has an upper surface that is coplanar with an upper surface of...


12/27/12 - 20120329270 - Surface repair structure and process for interconnect applications
A method is provided which includes providing a dielectric material having a dielectric constant of about 4.0 or less and at least one conductive material embedded therein, the at least one conductive material has an upper surface that is coplanar with an upper surface of the dielectric material and the...


12/27/12 - 20120326311 - Enhanced diffusion barrier for interconnect structures
Alternative methods of fabricating an interconnect structure in which an enhanced diffusion barrier including an in-situ formed metal nitride liner formed between an interconnect dielectric material and an overlying metal diffusion barrier liner are provided. In one embodiment, the method includes forming at least one opening into an interconnect dielectric...


12/13/12 - 20120313220 - High-nitrogen content metal resistor and method of forming same
A thin film metal resistor is provided that includes an in-situ formed metal nitride layer that is formed in a lower region of a deposited metal nitride layer. The in-situ formed metal nitride layer, together with the overlying deposited metal nitride layer, from a thin film metal resistor which has...


12/13/12 - 20120313194 - Semiconductor switching device and method of making the same
A switching device including a first dielectric layer having a first top surface, two conductive features embedded in the first dielectric layer, each conductive feature having a second top surface that is substantially coplanar with the first top surface of the first dielectric layer, and a set of discrete islands...


12/06/12 - 20120306048 - Electrically programmable metal fuse
A metal electrically programmable fuse (“eFuse”) includes a metal strip, having a strip width, of a metal line adjoined to wide metal line portions, having widths greater than the metal strip width, at both ends of the metal strip. The strip width can be a lithographic minimum dimension, and the...


11/01/12 - 20120273848 - Borderless contact structure employing dual etch stop layers
Each gate structure formed on the substrate includes a gate dielectric, a gate conductor, a first etch stop layer, and a gate cap dielectric. A second etch stop layer is formed over the gate structures, gate spacers, and source and drain regions. A first contact-level dielectric layer and a second...


10/18/12 - 20120264292 - Redundant metal barrier structure for interconnect applications
A redundant metal diffusion barrier is provided for an interconnect structure which improves the reliability and extendibility of the interconnect structure. The redundant metal diffusion barrier layer is located within an opening that is located within a dielectric material and it is between a diffusion barrier layer and a conductive...


10/18/12 - 20120261794 - Design structure for interconnect structure containing various capping materials for electrical fuse and other related applications
A design structure is provided for interconnect structures containing various capping materials for electrical fuses and other related applications. The structure includes a first interconnect structure having a first interfacial structure and a second interconnect structure adjacent to the first structure. The second interconnect structure has second interfacial structure different...


10/18/12 - 20120261793 - Electrical fuse and method of making the same
An improved electrical-fuse (e-fuse) device including a dielectric layer having a first top surface, two conductive features embedded in the dielectric layer and a fuse element. Each conductive feature has a second top surface and a metal cap directly on the second top surface. Each metal cap has a third...


09/13/12 - 20120228770 - Metal cap for back end of line (beol) interconnects, design structure and method of manufacture
A structure is provided with a metal cap for back end of line (BEOL) interconnects that substantially eliminates electro-migration (EM) damage, a design structure and a method of manufacturing the IC. The structure includes a metal interconnect formed in a dielectric material and a metal cap selective to the metal...


09/06/12 - 20120225549 - Redundancy design with electro-migration immunity and method of manufacture
An IC interconnect for high direct current (DC) that is substantially immune to electro-migration (EM) damage, and a method of manufacture of the IC interconnect are provided. A structure includes a cluster-of-via structure at an intersection between inter-level wires. The cluster-of-via structure includes a plurality of vias each of which...


08/16/12 - 20120208362 - Structure and process for metallization in high aspect ratio features
A high aspect ratio metallization structure is provided in which a noble metal-containing material is present at least within a lower portion of a contact opening located in a dielectric material and is in direct contact with a metal semiconductor alloy located on an upper surface of a material stack...


08/16/12 - 20120205804 - Method to fabricate copper wiring structures and structures formed tehreby
Techniques formation of high purity copper (Cu)-filled lines and vias are provided. In one aspect, a method of fabricating lines and vias filled with high purity copper with is provided. The method includes the following steps. A via is etched in a dielectric. The via is lined with a diffusion...


07/26/12 - 20120190187 - Pad bonding employing a self-aligned plated liner for adhesion enhancement
Two substrates are brought together and placed in a plating bath. In one embodiment, a conductive material is plated in microscopic cavities present at the interface between a first metal pad and a second metal pad to form at least one interfacial plated metal liner portion that adheres to a...


07/26/12 - 20120188002 - Modularized three-dimensional capacitor array
A modularized capacitor array includes a plurality of capacitor modules. Each capacitor module includes a capacitor and a switching device that is configured to electrically disconnect the capacitor. The switching device includes a sensing unit configured to detect the level of leakage of the capacitor so that the switching device...


07/26/12 - 20120187566 - Air-dielectric for subtractive etch line and via metallization
A method and structure is disclosed whereby multiple interconnect layers having effective air gaps positioned in regions most susceptible to capacitive coupling can be formed. The method includes providing a layer of conductive features, the layer including at least two line members disposed on a substrate and spaced from one...


07/26/12 - 20120187528 - Finfet fuse with enhanced current crowding
A method forms an eFuse structure that has a pair of adjacent semiconducting fins projecting from the planar surface of a substrate (in a direction perpendicular to the planar surface). The fins have planar sidewalls (perpendicular to the planar surface of the substrate) and planar tops (parallel to the planar...


07/05/12 - 20120171860 - Metal cap for back end of line (beol) interconnects, design structure and method of manufacture
A structure is provided with a metal cap for back end of line (BEOL) interconnects that substantially eliminates electro-migration (EM) damage, a design structure and a method of manufacturing the IC. The structure includes a metal interconnect formed in a dielectric material and a metal cap selective to the metal...


06/28/12 - 20120161334 - Redundancy design with electro-migration immunity and method of manufacture
An IC interconnect for high direct current (DC) that is substantially immune to electro-migration (EM) damage, and a method of manufacture of the IC interconnect are provided. A structure includes a cluster-of-via structure at an intersection between inter-level wires. The cluster-of-via structure includes a plurality of vias each of which...


06/21/12 - 20120153482 - Structure and methods of forming contact structures
A contact structure and a method of forming the contact structure. The structure includes: a silicide layer on and in direct physical contact with a top substrate surface of a substrate; an electrically insulating layer on the substrate; and an aluminum plug within the insulating layer. The aluminum plug has...


06/14/12 - 20120149191 - Metal cap with ultra-low k dielectric material for circuit interconnect applications
An interconnect structure is provided that has enhanced electromigration reliability without degrading circuit short yield, and improved technology extendibility. The inventive interconnect structure includes a dielectric material having a dielectric constant of about 3.0 or less. The dielectric material has at least one conductive material embedded therein. A noble metal...


05/03/12 - 20120104619 - Sublithographic patterning employing image transfer of a controllably damaged dielectric sidewall
A first low dielectric constant (low-k) dielectric material layer is lithographically patterned to form a recessed region having expose substantially vertical sidewalls, which are subsequently damaged to de-carbonize a surface portion at the sidewalls having a sublithographic width. A second low-k dielectric material layer is deposited to fill the recessed...


05/03/12 - 20120104470 - Replacement gate mosfet with raised source and drain
A disposable dielectric spacer is formed on sidewalls of a disposable material stack. Raised source/drain regions are formed on planar source/drain regions by selective epitaxy. The disposable dielectric spacer is removed to expose portions of a semiconductor layer between the disposable material stack and the source/drain regions including the raised...


04/12/12 - 20120086128 - Borderless interconnect line structure self-aligned to upper and lower level contact vias
A metal layer is deposited on a planar surface on which top surfaces of underlying metal vias are exposed. The metal layer is patterned to form at least one metal block, which has a horizontal cross-sectional area of a metal line to be formed and at least one overlying metal...


04/05/12 - 20120080771 - 3d via capacitor with a floating conductive plate for improved reliability
The present invention provides a 3D via capacitor and a method for forming the same. The capacitor includes an insulating layer on a substrate. The insulating layer has a via having sidewalls and a bottom. A first electrode overlies the sidewalls and at least a portion of the bottom of...


03/29/12 - 20120074520 - Electrical fuse structure and method of fabricating same
A high programming efficiency electrical fuse is provided utilizing a dual damascene structure located atop a metal layer. The dual damascene structure includes a patterned dielectric material having a line opening located above and connected to an underlying via opening. The via opening is located atop and is connected to...


03/22/12 - 20120068346 - Structure for nano-scale metallization and method for fabricating same
A method for forming structure aligned with features underlying an opaque layer is provided for an interconnect structure, such as an integrated circuit. In one embodiment, the method includes forming an opaque layer over a first layer, the first layer having a surface topography that maps to at least one...


01/19/12 - 20120012372 - Method and structure to improve the conductivity of narrow copper filled vias
Techniques for improving the conductivity of copper (Cu)-filled vias are provided. In one aspect, a method of fabricating a Cu-filled via is provided. The method includes the following steps. A via is etched in a dielectric. The via is lined with a diffusion barrier. A thin ruthenium (Ru) layer is...


11/24/11 - 20110285021 - Noble metal cap for interconnect structures
An interconnect structure that includes a dielectric material having a dielectric constant of about 3.0 or less is provided. This low k dielectric material has at least one conductive material having an upper surface embedded therein. The dielectric material also has a surface layer that is made hydrophobic prior to...


11/10/11 - 20110272765 - Mosfet gate and source/drain contact metallization
A MOSFET is described incorporating a common metal process to make contact to the source, drain and the metal gate respectively which may be formed concurrently with the same metal or metals....


10/20/11 - 20110254121 - Programmable anti-fuse structures with conductive material islands
Voltage programmable anti-fuse structures and methods are provided that include at least one conductive material island atop a dielectric surface that is located between two adjacent conductive features. In one embodiment, the anti-fuse structure includes a dielectric material having at least two adjacent conductive features embedded therein. At least one...


08/11/11 - 20110193230 - Formation of air gap with protection of metal lines
A method is provided for fabricating a microelectronic element having an air gap in a dielectric layer thereof. A dielectric cap layer can be formed which has a first portion overlying surfaces of metal lines, the first portion extending a first height above a height of a surface of the...


07/14/11 - 20110169127 - Structure for interconnect structure containing various capping materials for electrical fuse and other related applications
A design structure is provided for interconnect structures containing various capping materials for electrical fuses and other related applications. The structure includes a first interconnect structure having a first interfacial structure and a second interconnect structure adjacent to the first structure. The second interconnect structure has second interfacial structure different...


04/21/11 - 20110092067 - Air gap structure having protective metal silicide pads on a metal feature
A hard mask is formed on an interconnect structure comprising a low-k material layer and a metal feature embedded therein. A block polymer is applied to the hard mask layer, self-assembled, and patterned to form a polymeric matrix of a polymeric block component and containing cylindrical holes. The hard mask...


04/21/11 - 20110092031 - Efficient interconnect structure for electrical fuse applications
A semiconductor structure is provided that includes an interconnect structure and a fuse structure located in different areas, yet within the same interconnect level. The interconnect structure has high electromigration resistance, while the fuse structure has a lower electromigration resistance as compared with the interconnect structure. The fuse structure includes...


02/10/11 - 20110031623 - Interconnect structure and method for cu/ultra low k integration
A semiconductor structure is provided that includes a lower interconnect level including a first dielectric material having at least one conductive feature embedded therein; a dielectric capping layer located on the first dielectric material and some, but not all, portions of the at least one conductive feature; and an upper...


02/03/11 - 20110024909 - Bilayer metal capping layer for interconnect applications
The invention provides semiconductor interconnect structures that have improved reliability and technology extendibility. In the present invention, a second metallic capping layer is located on a surface of a first metallic cap layer which is, in turn, located on a surface of the conductive feature embedded within a first dielectric...


11/25/10 - 20100295181 - Redundant metal barrier structure for interconnect applications
A redundant metal diffusion barrier is provided for an interconnect structure which improves the reliability and extendibility of the interconnect structure. The redundant metal diffusion barrier layer is located within an opening that is located within a dielectric material and it is between a diffusion barrier layer and a conductive...


10/21/10 - 20100264543 - Interconnect structure
An interconnect structure and methods for forming semiconductor interconnect structures are disclosed. In one embodiment, the interconnect structure includes: a substrate including a first liner layer and a first metal layer thereover; a dielectric barrier layer over the first metal layer and the substrate; an inter-level dielectric layer over the...


07/15/10 - 20100176514 - Interconnect with recessed dielectric adjacent a noble metal cap
The invention comprises a copper interconnect structure that includes a noble metal cap with dielectric immediately adjacent the copper/noble metal cap interface recessed from the noble metal cap....


07/15/10 - 20100176512 - Structure and method for back end of the line integration
An improved semiconductor structure consists of interconnects in an upper interconnect level connected to interconnects in a lower interconnect level through use of a conductive protrusion located at the bottom of a via opening in an upper interconnect level, the conductive protrusion extends upward from bottom of the via opening...


06/10/10 - 20100143649 - High aspect ratio electroplated metal feature and method
Disclosed are embodiments of an improved high aspect ratio electroplated metal structure (e.g., a copper or copper alloy interconnect, such as a back end of the line (BEOL) or middle of the line (MOL) contact) in which the electroplated metal fill material is free from seams and/or voids. Also, disclosed...


04/08/10 - 20100084767 - Discontinuous/non-uniform metal cap structure and process for interconnect integration
An interconnect structure including a noble metal-containing cap that is present at least on some portion of an upper surface of at least one conductive material that is embedded within an interconnect dielectric material is provided. In one embodiment, the noble metal-containing cap is discontinuous, e.g., exists as nuclei or...


04/08/10 - 20100084766 - Surface repair structure and process for interconnect applications
Semiconductor interconnect structures including a surface-repair material, e.g., a noble metal or noble metal alloy, that fills hollow-metal related defects located within a conductive material are provided. The filling of the hollow-metal related defects with the surface repair material improves the electromigration (EM) reliability of the structure as well as...


02/18/10 - 20100038784 - Redundant barrier structure for interconnect and wiring applications, design structure and method of manufacture
A redundant diffusion barrier structure and method of fabricated is provided for interconnect and wiring applications. The structure can also be a design structure. The structure includes a first liner lining at least one of a trench and a via and a second liner deposited over the first liner. The...


02/18/10 - 20100038783 - Metal cap for back end of line (beol) interconnects, design structure and method of manufacture
A structure is provided with a metal cap for back end of line (BEOL) interconnects that substantially eliminates electro-migration (EM) damage, a design structure and a method of manufacturing the IC. The structure includes a metal interconnect formed in a dielectric material and a metal cap selective to the metal...


02/18/10 - 20100038782 - Nitrogen-containing metal cap for interconnect structures
An interconnect structure is provided that has enhanced electromigration reliability without degrading circuit short yield, and improved technology extendibility. The inventive interconnect structure includes a dielectric material having a dielectric constant of about 3.0 or less. The dielectric material has at least one conductive material embedded therein. A nitrogen-containing noble...


01/21/10 - 20100013043 - Crackstop structures and methods of making same
An integrated circuit chip and a method of fabricating an integrated circuit chip. The integrated circuit chip includes: a continuous first stress ring proximate to a perimeter of the integrated circuit chip, respective edges of the first stress ring parallel to respective edges of the integrated circuit chip; a continuous...


01/21/10 - 20100012950 - Crackstop structures and methods of making same
An integrated circuit chip and a method of fabricating an integrated circuit chip. The integrated circuit chip includes: a set of wiring levels stacked from a first wiring level to a last wiring level; and a respective void in each wiring level of two or more wiring levels of the...


12/31/09 - 20090321933 - Structure to facilitate plating into high aspect ratio vias
Improved high aspect ratio vias and techniques for the formation thereof are provided. In one aspect, a method of fabricating a copper plated high aspect ratio via is provided. The method comprises the following steps. A high aspect ratio via is etched in a dielectric layer. A diffusion barrier layer...


12/17/09 - 20090309226 - Interconnect structure for electromigration enhancement
An interconnect structure having enhanced electromigration resistance is provided in which a lower portion of a via opening includes a multi-layered liner. The multi-layered liner includes, from a patterned surface of a dielectric material outwards, a diffusion barrier, a multi-material layer and a metal-containing hard mask. The multi-material layer includes...


12/03/09 - 20090298281 - Interconnect structure with high leakage resistance
An interconnect structure is provided in which the conductive feature (i.e., conductive material) is not coplanar with the upper surface of the dielectric material, but instead the conductive material is recessed below an upper surface of the dielectric material. In addition to being recessed below the upper surface of the...


12/03/09 - 20090297759 - Stress locking layer for reliable metallization
Recrystallization and grain growth of metal, such as Cu, is achieved at higher anneal temperatures of 150° C. to 400° C., for example, for short anneal times of five to sixty minutes by forming a metal stress locking layer on the Cu before anneal and chemical-mechanical polishing. The stress locking...


11/26/09 - 20090289365 - Structure and process for conductive contact integration
A semiconductor structure including a highly reliable high aspect ratio contact structure in which key-hole seam formation is eliminated is provided. The key-hole seam formation is eliminated in the present invention by providing a densified noble metal-containing liner within a high aspect ratio contact opening that is present in a...


11/12/09 - 20090280636 - Methods of fabricating interconnect structures containing various capping materials for electrical fuse and other related applications
Methods are provided for fabricating interconnect structures containing various capping materials for electrical fuses and other related applications. The method includes forming a first interconnect structure having a first interfacial structure and forming a second interconnect structure adjacent to the first structure. The second interconnect structure is formed with a...


11/12/09 - 20090278260 - Redundancy design with electro-migration immunity and method of manufacture
An IC interconnect for high direct current (DC) that is substantially immune to electro-migration (EM) damage, a design structure of the IC interconnect and a method of manufacture of the IC interconnect is provided. The structure has electro-migration immunity and redundancy of design, which includes a plurality of wires laid...


11/12/09 - 20090278258 - Interconnect structure with a mushroom-shaped oxide capping layer and method for fabricating same
An interconnect structure is provided that includes a dielectric material 52′ having a dielectric constant of 4.0 or less and including a plurality of conductive features 56 embedded therein. The dielectric material 52′ has an upper surface 52r that is located beneath an upper surface of each of the plurality...


11/12/09 - 20090278229 - Efficient interconnect structure for electrical fuse applications
A semiconductor structure is provided that includes an interconnect structure and a fuse structure located in different areas, yet within the same interconnect level. The interconnect structure has high electromigration resistance, while the fuse structure has a lower electromigration resistance as compared with the interconnect structure. The fuse structure includes...


11/12/09 - 20090278228 - Design structure for interconnect structure containing various capping materials for electrical fuse and other related applications
A design structure is provided for interconnect structures containing various capping materials for electrical fuses and other related applications. The structure includes a first interconnect structure having a first interfacial structure and a second interconnect structure adjacent to the first structure. The second interconnect structure has second interfacial structure different...


10/08/09 - 20090250815 - Surface treatment for selective metal cap applications
Interconnect structures in which a noble metal-containing cap layer is present directly on a non-recessed surface of a conductive material which is embedded within a low k dielectric material are provided. It has been determined that by forming a hydrophobic surface on a low k dielectric material prior to metal...


09/03/09 - 20090218695 - Low contact resistance metal contact
A semiconductor structure and methods of making the same. The semiconductor structure includes a substrate having a silicide region disposed above a doped region, and a metal contact extending through the silicide region and being in direct contact with the doped region....


09/03/09 - 20090218691 - Bilayer metal capping layer for interconnect applications
The invention provides semiconductor interconnect structures that have improved reliability and technology extendibility. In the present invention, a second metallic capping layer is located on a surface of a first metallic cap layer which is, in turn, located on a surface of the conductive feature embedded within a first dielectric...


08/27/09 - 20090212433 - Structure and process for metallization in high aspect ratio features
A high aspect ratio metallization structure is provided in which a noble metal-containing material is present at least within a lower portion of a contact opening located in a dielectric material and is in direct contact with a metal semiconductor alloy located on an upper surface of a material stack...


08/13/09 - 20090200668 - Interconnect structure with high leakage resistance
An interconnect structure is provided in which the conductive feature (i.e., conductive material) is not coplanar with the upper surface of the dielectric material, but instead the conductive material is recessed below an upper surface of the dielectric material. In addition to being recessed below the upper surface of the...


08/06/09 - 20090194876 - Interconnect structure and method for cu/ultra low k integration
A semiconductor structure is provided that includes a lower interconnect level including a first dielectric material having at least one conductive feature embedded therein; a dielectric capping layer located on the first dielectric material and some, but not all, portions of the at least one conductive feature; and an upper...


08/06/09 - 20090194875 - High purity cu structure for interconnect applications
A structure and method of forming a high purity copper structure for interconnect applications is described. The structure includes a patterned dielectric material and at least one Cu-containing conductive material having an upper surface embedded within the dielectric material; and a diffusion barrier and a noble metal liner separating the...


07/30/09 - 20090189287 - Noble metal cap for interconnect structures
An interconnect structure that includes a dielectric material having a dielectric constant of about 3.0 or less is provided. This low k dielectric material has at least one conductive material having an upper surface embedded therein. The dielectric material also has a surface layer that is made hydrophobic prior to...


07/23/09 - 20090184400 - Via gouging methods and related semiconductor structure
Methods for via gouging and a related semiconductor structure are disclosed. In one embodiment, the method includes forming a via opening in a dielectric material, the via opening aligned with a conductor; forming a protective coating over the dielectric material and in the via opening; performing via gouging; and removing...


07/16/09 - 20090179328 - Barrier sequence for use in copper interconnect metallization
A method patterns at least one opening in a low-K insulator layer of a multi-level integrated circuit structure, such that a copper conductor is exposed at the bottom of the opening. The method then lines the sidewalls and the bottom of the opening with a first Tantalum Nitride layer in...


07/09/09 - 20090174075 - Simultaneous grain modulation for beol applications
The invention is directed to an improved semiconductor structure, such that within the same insulating layer, Cu interconnects embedded within the same insulating level layer have a different Cu grain size than other Cu interconnects embedded within the same insulating level layer....


06/11/09 - 20090148677 - High aspect ratio electroplated metal feature and method
Disclosed are embodiments of an improved high aspect ratio electroplated metal structure (e.g., a copper or copper alloy interconnect, such as a back end of the line (BEOL) or middle of the line (MOL) contact) in which the electroplated metal fill material is free from seams and/or voids. Also, disclosed...


06/04/09 - 20090140428 - Air gap structure having protective metal silicide pads on a metal feature
A hard mask is formed on an interconnect structure comprising a low-k material layer and a metal feature embedded therein. A block polymer is applied to the hard mask layer, self-assembled, and patterned to form a polymeric matrix of a polymeric block component and containing cylindrical holes. The hard mask...


05/07/09 - 20090117360 - Self-assembled material pattern transfer contrast enhancement
A non-photosensitive polymeric resist containing at least two immiscible polymeric block components is deposited on the planar surface. The non-photosensitive polymeric resist is annealed to allow phase separation of immiscible components and developed to remove at least one of the at least two polymeric block components. Nanoscale features, i.e., features...


04/30/09 - 20090108450 - Interconnect structure and method of making same
An interconnect structure and method of fabricating the same is provided. The interconnect structure is a highly reliable copper interconnect structure. The interconnect structure includes a planarized lower dielectric layer and a lower cap layer on the planarized lower dielectric layer. A copper material is formed in a trench of...


04/16/09 - 20090096108 - Structure and methods of forming contact structures
Methods and a structure. A method of forming contact structure includes depositing a silicide layer onto a substrate; depositing an electrically insulating layer over a first surface of the silicide layer; forming a via through the insulating layer extending to the first surface; depositing an electrically conductive layer covering a...


03/26/09 - 20090079077 - Interconnect structure with a via gouging feature absent profile damage to the interconnect dielectric and method of fabricating same
An interconnect structure including a gouging feature at the bottom of the via openings and a method of forming the same, which does not introduce either damages caused by Ar sputtering into the dielectric material that includes the via and line openings, nor plating voids into the structure are provided....


03/19/09 - 20090072406 - Interconnect structure with improved electromigration resistance and method of fabricating same
An interconnect structure in which the electromigration resistance thereof is improved without introducing a gouging feature within the interconnect structure is provided. The interconnect structure includes a metallic interfacial layer that is at least horizontally present at the bottom of an opening located within a second dielectric material that is...


03/05/09 - 20090057818 - Methods and systems involving electrically programmable fuses
An electrically programmable fuse comprising a cathode member, an anode member, and a link member, wherein the cathode member, the anode member, and the link member each comprise one of a plurality of materials operative to localize induced electromigration in the programmable fuse....


02/05/09 - 20090035954 - Interconnect structure with grain growth promotion layer and method for forming the same
In general, the present invention provides an interconnect structure and method for forming the same. This present invention discloses an interconnect structure includes a Cu seeding layer embedded between a diffusion barrier layer and a grain growth promotion layer. Specifically, under the present invention, a diffusion barrier layer is formed...


International Business Machines Corporation

Archived*
(*May have duplicates - we are upgrading our archive.)

20130001789 - Interconnect structure with improved dielectric line to via electromigration resistant interfacial layer and method of fabricating same
20130005137 - Barrier sequence for use in copper interconnect metallization


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