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  Chemical mechanical polishing compositions for metal and associated materials and method of using sameUSPTO Application #: 20060160475Title: Chemical mechanical polishing compositions for metal and associated materials and method of using same Abstract: A chemical mechanical polishing slurry composition and method for using the slurry composition for polishing copper, barrier material and dielectric material that comprises first and second-step slurries. The first-step slurry has a high removal rate on copper and a low removal rate on barrier material. The second-step slurry has a high removal rate on barrier material and a low removal rate on copper and dielectric material. The first slurry comprises at least an organic polymeric abrasive. (end of abstract)
Agent: Moore & Van Allen PLLC - Research Triangle Park, NC, US Inventors: Ying Ma, William Wojtczak, Cary Regulski, Thomas H. Baum, David D. Bernhard, Deepak Verma USPTO Applicaton #: 20060160475 - Class: 451041000 (USPTO) Related Patent Categories: Abrading, Abrading Process, Glass Or Stone Abrading The Patent Description & Claims data below is from USPTO Patent Application 20060160475. Brief Patent Description - Full Patent Description - Patent Application Claims
TECHNICAL FIELD OF THE INVENTION [0001] The present invention relates generally to the chemical mechanical polishing of semiconductor devices systems and methods, and more particularly, to a formulation and method for use in polishing metal films in semiconductor interconnection processes. BACKGROUND OF THE INVENTION [0002] The present invention relates to a chemical mechanical polishing composition for surfaces of a semiconductor wafer, and more particularly, to a chemical mechanical polishing slurry and a method for using the slurry to remove and polish copper containing materials, barrier materials and dielectric materials layered on semiconductor wafer surfaces. [0003] Semiconductor wafers are used to form integrated circuits. The semiconductor wafer typically includes a substrate, such as silicon, upon which dielectric materials, barrier materials, and metal conductors and interconnects are layered. These different materials have insulating, conductive or semi-conductive properties. Integrated circuits are formed by patterning regions into the substrate and depositing thereon multiple layers of dielectric material, barrier material, and metals. [0004] In order to meet the higher speeds required in large scale integration (LSI), semiconductor manufacturers are looking to copper and its alloys as interconnect materials due to its decreased resistivity. Copper is also less vulnerable to electromigration than other metals such as aluminum and less likely to fracture under stress. [0005] In conventional deposition, a layer of metal and a layer of a masking material called photoresist are deposited on a silicon wafer. Unwanted metal is then etched away with an appropriate chemical, leaving the desired pattern of wires or vias. Next, the spaces between the wires or vias are filled with silicon dioxide (an insulator), and finally the entire wafer surface is polished to remove excess insulator. In copper deposition the damascene method is used wherein an oxide layer is first deposited and the pattern of wires or vias is formed by etching the oxide. The metal is then deposited second. [0006] As successive layers are deposited across previously patterned layers of an integrated circuit, elevational disparity or topography develops across the surface of each layer. If left unattended, the elevational disparities in each level of an integrated circuit can lead to various problems. For example, when dielectric, conductive, or semiconductive material is deposited over a topological surface having elevationally raised and recessed regions, step coverage problems may arise. Step coverage is defined as a measure of how well a film conforms over an underlying step and is expressed by the ratio of the minimum thickness of a film as it crosses a step to the nominal thickness of the film over horizontal regions. [0007] Typically for copper technology, the layers that are removed and polished consist of a copper layer (about 1-1.5 .mu.m thick) on top of a thin copper seed layer (about 0.05-0.15 .mu.m thick). These copper layers are separated from the dielectric material surface by a layer of barrier material (about 50-300 .ANG. thick). [0008] In order to obtain the correct patterning, excess material used to form the layers on the substrate must be removed and or planarized. Further, to obtain efficient circuits, it is important to have a flat or planar semiconductor wafer surface. Thus, it is necessary to polish certain surfaces of a semiconductor wafer. [0009] Chemical Mechanical Polishing or Planarization ("CMP") is a process in which material is removed from a surface of a semiconductor wafer, and the surface is polished (planarized) by coupling a physical process such as abrasion with a chemical process such as oxidation or chelation. In its most rudimentary form, CMP involves applying slurry, a solution of an abrasive and an active chemistry, to a silicon wafer or polishing pad that buffs the surface of a semiconductor wafer to achieve the removal, planarization, and polishing process. [0010] One key to obtaining good uniformity across the wafer surface is by a polishing formulation that has the appropriate selectivity for the material(s) to be removed. Good slurry distribution and uniform distribution of mechanical force are also key to obtaining good planarity. If appropriate film removal selectivity is not maintained dishing of copper and/or erosion of the dielectric may occur. Dishing may occur when the copper and barrier removal rates are disparate or when the chemistry is too active for the metal interconnect layer. Erosion occurs when the local dielectric removal rate is much higher than the metal rate (see FIGS. 1-5). [0011] Typical commercial CMP slurries used to remove overfill material and polish semiconductor wafer surfaces have a barrier material removal rate below 500 .ANG./min. Further, these slurries have a copper to barrier material removal rate selectivity of greater than 4:1. This disparity in removal rates during the removal and polishing of the barrier material results in significant dishing of copper on the surface of the semiconductor wafer and/or poor removal of the barrier material. [0012] As a potential solution, copper CMP often employs a two-step slurry approach. The slurry used in the first step is typically used to remove and planarize bulk copper and as such has a high copper removal rate, (e.g. 4000 .ANG./min) and a comparatively low barrier material removal rate (e.g. 500 .ANG./min). The slurry used in the second step is used for the barrier breakthrough step and finishing and as such has a relatively high barrier material removal rate (e.g. 1000 .ANG./min), comparable or lower removal rate for copper and low removal rate on the dielectric material, (e.g. the rates for copper and dielectric (thermal oxide) should be lower than 500 .ANG./min). [0013] Currently, commercially available copper slurries use particles such as fumed or precipitated silica or alumina as abrasives. These abrasives typically have large particle size distributions when suspended in the slurries. Particles of fumed alumina and silica have diameters around 700 nm and particle size distributions of >1 .mu.m. Wide particle size distribution may significantly impact the planarization efficiency. [0014] Fumed or precipitated silica or alumina may also agglomerate to form larger, dense, hard particles or agglomerated precipitates over time. (See U.S. Pat. No. 5,527,423 to Neville, et al.). This produces defects in the form of scratches, voids, defects or pits on the polished wafer surface. [0015] Further, the abrasives are inorganic oxide particles that have high hardness. As a result, defects in the form of micro-scratches are produced on copper surfaces during and after polishing. The scratches occur due to the solid abrasive, in particular alumina, which is the main material used as a metal polishing abrasive. Slurry remains behind in the micro-scratches causing the semiconductor device to fail. Micro scratches and poor planarization efficiency result in integrated circuits with increased defects and a lower yield. [0016] Current second step slurries suffer from a low selectivity of barrier to metal, the best selectivity being about 6 to 1, while the selectivity of barrier to dielectric is in the range of from about 2 to 27. (See U.S. Pat. Nos. 6,063,306 to Kaufman, et al.; 5,676,587 to Landers, et al.; 6,001,730 to Farkas, et al.; and 6,242,351 to Li, et al.). [0017] Therefore, it is one object of the present invention to provide an improved slurry composition using an abrasive having a moderate hardness to remove a softer metal oxide layer while keeping the harder barrier layer and thermal oxide layer relatively intact. [0018] It is a further object of this invention to provide an improved two step slurry approach using a first polishing slurry having a high removal rate on metal and a high selectivity of metal to barrier and a second slurry also called a barrier break-through step having a high removal rate on barrier and a low to moderate removal rate on copper and dielectric. [0019] It is a further object of the present invention to provide a stable first-step polishing slurry comprising an abrasive that does not agglomerate over time to form hard, dense sediment. [0020] A still further object of the present invention is to provide a stable first-step polishing slurry comprising a moderately hard abrasive having a minimal particle size distribution. [0021] These and other objects and advantages of the invention will be apparent to those skilled in the art upon reading the following detailed description and upon reference to the drawings. SUMMARY OF THE INVENTION Continue reading... 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