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  Chemical mechanical polish with multi-zone abrasive-containing matrixUSPTO Application #: 20060079159Title: Chemical mechanical polish with multi-zone abrasive-containing matrix Abstract: Chemical mechanical polish (CMP) devices, CMP systems, methods of CMP, and methods of manufacturing CMP devices. A CMP device comprises a plurality of zones, with each zone having a matrix of fixed abrasive features disposed therein. The abrasive-containing matrix within each zone has material removal properties that differ from the material removal properties of the abrasive-containing matrixes of the other zones. The material removal property differences of the abrasive-containing matrixes of the zones may achieved by using different abrasive materials, densities, heights, or shapes, or combinations thereof, of the fixed abrasive features within the zones, or by using physical or chemical conditioning. When the novel CMP device is used to planarize a semiconductor wafer, a substantially planar surface with an improved CMP profile results. (end of abstract) Agent: Slater & Matsil LLP - Dallas, TX, US Inventors: Markus Naujok, Laertis Economikos USPTO Applicaton #: 20060079159 - Class: 451285000 (USPTO) Related Patent Categories: Abrading, Machine, Rotary Tool, Rotary Disk, Work Rotating, Rotary Work Holder The Patent Description & Claims data below is from USPTO Patent Application 20060079159. Brief Patent Description - Full Patent Description - Patent Application Claims
TECHNICAL FIELD [0001] The present invention relates generally to manufacturing processes for semiconductor devices, and more particularly to chemical mechanical polish (CMP) processes. BACKGROUND [0002] Semiconductor devices are manufactured by depositing many different types of material layers over a semiconductor workpiece or wafer, and patterning the various material layers using lithography. The material layers typically comprise thin films of conductive, semiconductive and insulating materials that are patterned to form integrated circuits (IC's). In many integrated circuit designs, the various material layers are planarized before depositing subsequent material layers. [0003] There may be a plurality of transistors, memory devices, switches, conductive lines, diodes, capacitors, logic circuits, and other electronic components formed on a single semiconductor die or chip. Semiconductor technology has experienced a trend towards miniaturization, to meet the demands of product size reduction, improved device performance, and reduced power requirements in the end applications that semiconductors are used in, for example. [0004] In the past, integrated circuits contained only a relatively small number of devices per chip, and the devices could be easily interconnected. However, in more recent integrated circuit designs, there may be millions of devices on a single chip, resulting in the need for multilevel interconnect systems, wherein the area for interconnect lines is shared among two or more material levels. [0005] As the number of interconnect layers in integrated circuits has increased, the planarization of dielectric and metal layers has become more critical. In the past, planarization techniques such as thermal flow, sacrificial-resist etch-back, and spin-on glass were adequate to planarize interconnect systems. However, these techniques provide only a limited degree of smoothing and local planarization. For global planarization of a semiconductor wafer, chemical-mechanical polishing (CMP) is typically used. [0006] A schematic drawing of a prior art CMP polishing tool 100 is shown in FIG. 1. The back side of a semiconductor wafer 102 is mounted on a carrier 106. Using the carrier 106, the face or top surface of the semiconductor wafer 102 is pressed against a platen 108 rotating in a direction 105 containing a polishing pad 104. The carrier 106 is also rotated in a direction 103. In some CMP tools, the carrier 106 is also moved laterally in relation to the platen 108, e.g., in a direction 107, as shown. An abrasive-containing slurry may be dripped onto the platen 108, saturating the polishing pad 104. The polishing pad 104 may include an abrasive material formed thereon. The type of abrasive material used is dependant upon the material layer to be planarized; for example, ceria or silicon oxide are often used to planarize oxide material layers, and aluminum oxide is often used to planarize copper. [0007] In a CMP process, elevated features on the wafer 102 are selectively removed, e.g., material from high elevation features is removed more rapidly than material at lower elevations, resulting in reduced topography. The process is referred to as "chemical-mechanical polishing" because material is removed from the wafer 102 by mechanical polishing, assisted by chemical action. [0008] CMP is a critical process in the fabrication of integrated circuits, particularly for sub-micron IC's. Multilevel interconnections having eight or more levels of metal are possible using CMP, because CMP avoids the problem of metal thinning over steep topographies in multilevel interconnect structures. CMP provides a more flat wafer surface than other planarization methods, which increases the depth of focus budget available for lithography, allowing designers to employ smaller critical dimensions, thus reducing chip sizes without decreasing yield, providing a cost advantage. Also, CMP reduces defect density. [0009] One problem with CMP is the non-uniformity of film thickness across a wafer. The non-uniformity may be originated through non-planar incoming layers into the CMP process, or through a non-uniform material removal in the CMP process. A non-uniform top surface of a wafer may be caused in the CMP process by a combination of the tool, e.g., polish head, the consumables, e.g., slurry, pad, and/or the process conditions, e.g., pressure, rotation speed ratios, etc. An example of a wafer 102 having a non-uniform top surface after a CMP process is shown in a cross-sectional view in FIG. 2. The wafer 102 is thinner at the middle 112 than at the edges 110. [0010] FIG. 3 is a graph depicting a typical removal profile using a conventional CMP process, wherein the edge region has a lower removal rate than the center region. Graph 114 shows the CMP removal rate of a thermal oxide at a psi of 1.5, and graph 116 shows the CMP removal rate of oxide at a psi of 2.0, wherein "0" on the x axis indicates the center of the wafer. The removal rate is lower at the edges of the wafer. [0011] One approach to obtain planar polish results is to use a polish head that allows the application of different pressure ranges in different zones of the head to the wafer. Depending on the applied pressures and pressure ratios between the various pressure zones, incoming or process induced non-uniformities can be compensated for. However, there are disadvantages of using such a multi-zone pressure head for CMP. Such a CMP system is complex, and there is a limitation for its use on certain profiles. Also, residuals may remain on the edges of the substrate after the CMP process. [0012] What is needed in the art is a CMP process that results in improved uniformity of a semiconductor wafer surface. SUMMARY OF THE INVENTION [0013] These and other problems are generally solved or circumvented, and technical advantages are generally achieved, by preferred embodiments of the present invention which provide novel CMP devices or pad/tool combination for planarizing semiconductor wafers. [0014] In accordance with a preferred embodiment of the present invention, a CMP device for planarizing a semiconductor wafer includes a first zone, the first zone comprising a first material removal property, and at least one second zone, the at least one second zone comprising a second material removal property. The second material removal property is different than the first material removal property. [0015] In accordance with another preferred embodiment of the present invention, a method of planarizing a top surface of a semiconductor wafer includes providing a CMP device, the CMP device comprising a first zone, the first zone comprising a first material removal property, the CMP device includes at least one second zone, the at least one second zone comprising a second material removal property, wherein the second material removal property is different than the first material removal property. The method includes providing a semiconductor wafer, the semiconductor wafer having a top surface, and polishing the top surface of the semiconductor wafer with the CMP device. [0016] In accordance with yet another preferred embodiment of the present invention, a method of manufacturing a CMP device includes providing a backing material, attaching a plurality of first fixed abrasive features to the backing material in a first zone, the first zone comprising a first material removal property, and attaching a plurality of second fixed abrasive features to the backing material in at least one second zone, the at least one second zone comprising a second material removal property. The second material removal property is different than the first material removal property. [0017] Advantages of embodiments of the present invention include providing a CMP pad or web having zones with non-uniform fixed abrasive features formed thereon that can produce a more planar surface, when used to planarize a semiconductor wafer. Semiconductor wafers with improved CMP profiles are achieved by planarizing with the novel CMP device described herein. [0018] The foregoing has outlined rather broadly the features and technical advantages of embodiments of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of embodiments of the invention will be described hereinafter, which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiments disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS [0019] For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: [0020] FIG. 1 is a schematic drawing of a prior art CMP tool; Continue reading... Full patent description for Chemical mechanical polish with multi-zone abrasive-containing matrix Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Chemical mechanical polish with multi-zone abrasive-containing matrix patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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