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Chemical etch solution and technique for imaging a device's shallow junction profileRelated Patent Categories: Etching A Substrate: Processes, Nongaseous Phase Etching Of SubstrateChemical etch solution and technique for imaging a device's shallow junction profile description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20080011717, Chemical etch solution and technique for imaging a device's shallow junction profile. Brief Patent Description - Full Patent Description - Patent Application Claims
[0001] This application is a divisional of application Ser. No. 11/028,833, filed Jan. 4, 2005. TECHNICAL FIELD OF THE INVENTION [0002] The present invention is directed in general to the manufacture of semiconductor devices, and, more specifically, to a chemical etch solution and technique for imaging device's shallow junction profile. BACKGROUND OF THE INVENTION [0003] The continuing push to produce faster microelectronic devices with lower power consumption has resulted in the miniaturization of such devices. In particular, smaller gate length and channel lengths are conducive to the low voltage and faster operation of transistor devices, such as complementary metal oxide semiconductor (CMOS) transistors. However, with shrinking process geometries, a number of new design problems arise. [0004] For instance, as gate dimensions are reduced, it has become necessary to adjust and better control the dimensions of the channel and doped regions of the substrate that are associated with the gate. This is necessary to prevent a number of short channel effects such as, threshold voltage variation, drain induced barrier lowering (DIBL), punch-through, leakage currents, hot carrier injection, and mobility degradation. [0005] Consider, for instance, the dimensions of shallow junctions and pocket region structures. Shallow junctions, also referred to as source drain extensions, or light or medium-doped drain (LDD and MDD, respectively) regions, are implanted as extensions to the larger and more heavily doped source and drain regions, to reduce hot carrier injection-induced damage to gate dielectric layers and improve short channel effects. Hot carriers, electrons with higher than average energy, form because of the stronger electric fields produced in small transistor device geometries. Shallow junctions, implanted before sidewall formation and source and drain implantation, provide a doping gradient between the source and drain regions and the channel. The lowered electric field in the vicinity of the channel region of such devices reduces the formation of hot carriers. [0006] Sub-0.1 micron transistor devices are also highly susceptible to leakage currents, or punch-through, when the transistor is off. These conditions can arise when the shallow junctions and the source/drains are not properly formed. Thus, leakage currents can be reduced if the shallow junctions are formed with well-defined boundaries, as exemplified by an abrupt decrease in dopant concentration, to support low-voltage operation of the transistor and to define the width of the channel region of the transistor. [0007] Unfortunately, however, it can be very difficult to ascertain any irregularities in these shallow junctions or source/drain areas using standard imaging techniques. This is largely attributable to the fact that these shallow junctions do not show up in the cross section scans of an imaging tool, such as a scanning electron microscope (SEM) or a transmission electron microscope (TEM). Thus, it can be very difficult to ascertain with any degree of certainty what structural defects or irregularities might exist in the junction or gate areas of the microelectronics device. [0008] Accordingly, what is needed in the art is an improved method of obtaining an image of the junctions areas of a microelectronics device. SUMMARY OF THE INVENTION [0009] To address the above-discussed deficiencies of the prior art, the present invention provides a method of imaging a shallow junction profile in a microelectronics device. In one embodiment, the method comprises cleaning a sample of a microelectronics device to be imaged with a first solution comprising hydrofluoric acid, an inorganic acid and water, exposing the sample to a second solution comprising hydrofluoric acid, an inorganic acid and an organic acid, wherein the second solution forms a contrast between different regions within the sample, and producing an image of the sample. [0010] In another embodiment, there is provided a method of manufacturing an integrated circuit. This particular embodiment comprises forming at least a portion of an integrated circuit on a microelectronic device substrate using a fabrication process and preparing a test sample from the portion of the integrated circuit. The test sample is exposed to a contrast solution comprising hydrofluoric acid, an inorganic acid and an organic acid, wherein the contrasting solution forms a contrast between different regions within the test sample. An image of the contrasted test sample is produced to determine if the test sample falls within a specified parameter. If the test sample falls outside the specified parameter, the fabrication process is adjusted to bring an integrated circuit produced by the fabrication process within the specified parameter. The adjusted fabrication process is then used to fabricate an operative integrated circuit. [0011] The foregoing has outlined preferred and alternative features of the present invention so that those of ordinary skill in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS [0012] The invention is best understood from the following detailed description when read with the accompanying FIGURES. It is emphasized that in accordance with the standard practice in the semiconductor industry, various features may not be drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. Reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: [0013] FIG. 1 illustrates a partial sectional view of microelectronics device at an early stage of manufacture and with which the present invention can be implemented [0014] FIG. 2 illustrates an image of junction regions of a microelectronics device taken with a transmission electron microscope after being prepared in accordance with the principles of the present invention; [0015] FIG. 3 illustrates an image of a sample of a microelectronics device wherein the present invention has not been utilized, thereby showing a lack of contrast between the junction regions and the well; [0016] FIG. 4 illustrates an image of a well region of a microelectronics device taken with a scanning electron microscope after being prepared in accordance with the principles of the present invention; and [0017] FIG. 5 is a partial sectional view of an integrated circuit that can be constructed using the present invention. DETAILED DESCRIPTION [0018] Turing initially to FIG. 1, there is illustrated a partial, sectional view of an exemplary integrated circuit 100 at the first metal level that is located over a device level. At this point of manufacture, the integrated circuit 100 is of conventional design and includes a substrate 110, such as a microelectronics substrate on which sub-micron devices can be built. The substrate 110 may be configured to serve as a well region for the integrated circuit 100, or it might have an epitaxial layer 115 located thereover in which wells 120 are formed. The wells 120 may be complementary wells, such as an N-type well and a P-type well, respectively, however, other well known doping configurations are also applicable. The integrated circuit 100 further comprises conventional transistors 125, such as complementary NMOS and PMOS transistors, that may include gates 130 and source/drain regions 135, 137, respectively. These source/drain regions 135, 137 are often referred to as junctions and can often include lightly doped and halo extensions 138. The spacing between these junctions under the gate define the channel length, and this spacing, as well as their doping profiles, can have critical implications on the operation of the microelectronics device 100. As such, it is highly beneficial that these junctions be as close to design specifications as possible. Also shown in FIG. 1 are contacts 140, which connect the gates 130 and source/drains 135, 137 of each of the transistors 125 to overlying metal interconnect structures 145 formed on an interlevel dielectric layer 147. [0019] The present invention provides a unique method for imaging the doped junction areas of the microelectronic device 100. In an advantageous embodiment, the sample may be sectioned by using a focused ion beam. It has been found that in some cases, the focused ion beam process can contaminate the sample with gallium. With the present invention, it has presently been found that contaminants, including gallium, can interfere with or inhibit obtaining a good contrast image of the microelectronics device 100, particularly in the junction region of the device. Thus, in one embodiment, the present invention recognizes the need to remove such contaminants from the sample to obtain a high quality image of the cross section of the microelectronics device 100 for more accurate analysis. It should be understood, however, that in those instances where the sample can be sectioned by methods that significantly reduce such contaminants, the removal step may not be necessary. Continue reading about Chemical etch solution and technique for imaging a device's shallow junction profile... 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