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  Charge trapping dielectric structure for non-volatile memoryUSPTO Application #: 20060113586Title: Charge trapping dielectric structure for non-volatile memory Abstract: An integrated circuit structure comprises a bottom dielectric layer on a substrate, a middle dielectric layer, and a top dielectric layer. The middle dielectric layer has a top surface and a bottom surface, and comprises a plurality of materials. Respective concentration profiles for at least two of the plurality of materials between the top and bottom surfaces are non-uniform and arranged to induce a variation in energy gap between the top and bottom surfaces. The variation in energy gap establishes an electric field between the top and bottom surfaces tending to oppose charge motion toward at least one of the top and bottom surfaces and prevent resultant charge leakage. (end of abstract) Agent: Macronix C/o Haynes Beffell & Wolfeld LLP - Half Moon Bay, CA, US Inventor: Szu-Yu Wang USPTO Applicaton #: 20060113586 - Class: 257324000 (USPTO) Related Patent Categories: Active Solid-state Devices (e.g., Transistors, Solid-state Diodes), Field Effect Device, Having Insulated Electrode (e.g., Mosfet, Mos Diode), Variable Threshold (e.g., Floating Gate Memory Device), Multiple Insulator Layers (e.g., Mnos Structure) The Patent Description & Claims data below is from USPTO Patent Application 20060113586. Brief Patent Description - Full Patent Description - Patent Application Claims
BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to charge trapping dielectric structures and to non-volatile memory based on such structures. [0003] 2. Description of Related Art [0004] Electrically programmable and erasable non-volatile memory technologies based on charge storage structures known as EEPROM and flash memory are used in a variety of modern applications. A number of memory cell structures are used for EEPROM and flash memory. As the dimensions of integrated circuits shrink, greater interest is arising for memory cell structures based on charge trapping dielectric layers, because of the scalability and simplicity of the manufacturing processes. Memory cell structures based on charge trapping dielectric layers include structures known by the industry names NROM, SONOS, and PHINES, for example. These memory cell structures store data by trapping charge in a charge trapping dielectric layer, such as silicon nitride. As negative charge is trapped, the threshold voltage of the memory cell increases. The threshold voltage of the memory cell is reduced by removing negative charge from the charge trapping layer. [0005] One problem associated with charge trapping structures used in non-volatile memory is data retention. For commercial products it is desirable for such devices to hold data for at least ten years without loss. However, leakage of trapped charge occurs in such devices due to defects in the materials which accumulate over long use, or which are inherent in the structures. [0006] It is desirable to provide charge trapping structures for non-volatile memory with improved charge retention characteristics. SUMMARY OF THE INVENTION [0007] The present invention provides an integrated circuit structure and a method for manufacturing an integrated circuit structure that comprises a bottom dielectric layer on a substrate, a middle dielectric layer, and a top dielectric layer. The middle dielectric layer has a top surface and a bottom surface, and comprises a plurality of materials. Respective concentration profiles for at least two of the plurality of materials between the top and bottom surfaces are non-uniform and arranged to induce a variation in energy gap between the top and bottom surfaces. The variation in energy gap establishes an electric field between the top and bottom surfaces tending to oppose charge motion toward at least one of the top and bottom surfaces and prevent resultant charge leakage. In embodiments of the structure, the bottom dielectric layer and the top dielectric layer are characterized by respective energy gaps at the interfaces with the top and bottom surfaces of the middle dielectric layer that are greater than a maximum energy gap in the middle dielectric layer, and in some embodiments greater than the energy gap levels in the middle dielectric layer at such interfaces. Various embodiments of the integrated circuit structure provide for a variation in energy gap which includes a minimum energy gap spaced away from the top and bottom surfaces, such as in a central region of the middle dielectric layer, and maximum energy gaps near to both of the top and bottom surfaces. Other embodiments provide for variation in energy gap which includes a minimum energy gap near the top surface of the middle dielectric layer and a maximum energy gap near the bottom surface, or vice versa. In some embodiments, the variation in energy gap is substantially monotonically increasing from one to the other of the top and bottom surfaces. [0008] The integrated circuit structure is used for example in non-volatile charge storage flash memory devices, where the middle dielectric layer acts as the charge storage layer. In yet other embodiments, an integrated circuit structure is used as an interpoly dielectric layer in a floating gate memory cell. Thus, embodiments of the technology described include unique memory cells incorporating the top, middle and bottom dielectric layers described above. [0009] Materials suitable for the middle dielectric layer include a combination of silicon, oxygen and nitrogen, like silicon oxynitride SiO.sub.xN.sub.y, where x and y are variable. The materials are arranged for example so that the concentration in a first half of the middle dielectric layer near the top dielectric layer of material tending to decrease the energy gap (like nitrogen in a silicon oxynitride) is greater than the concentration of such material in a second half of the middle dielectric layer near the bottom dielectric layer, and so that the material tending to increase the energy gap (like oxygen in a silicon oxynitride) has a concentration that is lower in the first half of the middle dielectric layer near the top dielectric layer, and higher in a second half of the middle dielectric layer near the bottom dielectric layer. For example, for an embodiment comprising a combination of silicon, oxygen and nitrogen, the concentration of oxygen decreases from the bottom surface of the middle dielectric layer to the top surface of the middle dielectric layer, and the concentration of nitrogen increases from the bottom surface of the middle dielectric layer to the top surface. This structure opposes charge movement toward the bottom surface of the middle dielectric layer. In yet another embodiment, the materials are arranged so that the maximum energy gap is near the top surface of the middle dielectric layer and the minimum energy gap is near the bottom surface, to oppose charge movement towards the top surface. The materials can also be arranged to oppose charge movement towards both the top and bottom surfaces, by establishing a minimum energy gap in a central region of the middle dielectric layer, with maximums near both the top and bottom surfaces. [0010] Methods for manufacturing a middle dielectric layer for the structures described herein include depositing a sequence of thin films having varying concentrations of materials and/or varying combinations of materials using techniques like atomic layer deposition, chemical vapor deposition, and so on. In embodiments where the middle dielectric layer comprises silicon oxynitride, a method for manufacturing includes formation of a first film of silicon oxynitride with a nominal concentration of silicon, oxygen and nitrogen, followed by exposing the first film to nitrogen in a manner that causes incorporation of nitrogen into the structure near the top surface of the middle dielectric layer. The resulting structure can be annealed to smooth out the concentration profiles. In another embodiment, where the middle dielectric layer comprises silicon oxynitride, a method for manufacturing includes forming a first film of silicon oxynitride on the bottom dielectric, and forming a film of silicon nitride on the first film, followed by annealing the first and second films to smooth out the transition between the silicon oxynitride and the silicon nitride. [0011] Other aspects and advantages of the present invention can be seen on review of the drawings, the detailed description and the claims, which follow. BRIEF DESCRIPTION OF THE DRAWINGS [0012] FIG. 1 is a simplified diagram of an integrated circuit including a charge storage memory cell array, where the memory cells have a dielectric layer with an energy gap gradient to oppose charge leakage. [0013] FIG. 2 is a simplified diagram of a charge trapping memory cell including a dielectric layer with an energy gap gradient to oppose charge leakage. [0014] FIG. 3 is a simplified energy gap diagram for a prior art charge trapping dielectric structure. [0015] FIG. 4 is a simplified energy gap diagram for a charge trapping dielectric structure, including a middle dielectric layer with an energy gap gradient to oppose charge leakage. [0016] FIG. 5 is a simplified illustration for the purposes of describing a method for manufacturing a charge trapping dielectric structure, including a middle dielectric layer with an energy gap gradient to oppose charge leakage. [0017] FIG. 6 is a simplified illustration for the purposes of describing another method for manufacturing a charge trapping dielectric structure, including a middle dielectric layer with an energy gap gradient to oppose charge leakage. [0018] FIG. 7 is a graph of concentration of materials from a bottom surface to a top surface of a middle dielectric layer in a charge trapping dielectric structure for a simplified embodiment. [0019] FIG. 8 is a simplified energy gap diagram for a charge trapping dielectric structure, including a middle dielectric -layer-with an-energy gap minimum in a central region, and energy gap maximums near both the top and bottom surfaces, to oppose charge leakage. [0020] FIG. 9 is a simplified diagram of a floating gate memory cell including a dielectric layer with an energy gap gradient to oppose charge leakage. DETAILED DESCRIPTION Continue reading... Full patent description for Charge trapping dielectric structure for non-volatile memory Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Charge trapping dielectric structure for non-volatile memory patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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