Charge trapping device

Title: Charge trapping device

Related Patent Categories: Active Solid-state Devices (e.g., Transistors, Solid-state Diodes), Field Effect Device, Having Insulated Electrode (e.g., Mosfet, Mos Diode)

Brief Patent Description - Full Patent Description - Patent Claims

The Patent Description & Claims data below is from USPTO Patent Application 20060197122, Charge trapping device.

1. A silicon based semiconductor device comprising: a silicon based substrate; a channel region in the silicon based substrate for carrying a device current consisting of charge carriers between a source region and a drain region; a gate region for receiving a gate bias voltage to control a density of said charge carriers in said channel region available for said device current; a trapping region located proximate to said channel region, said trapping region being configured for trapping charge carriers and altering said density of charge carriers in said channel region; wherein said density of charge carriers in said channel region available for said device current is also controllable by a drain bias voltage applied to said drain region, such that said drain bias voltage can reduce said density of charge carriers and turn off the silicon based semiconductor device.

2. The silicon based semiconductor device of claim 1, wherein said channel exhibits negative differential resistance.

3. The silicon based semiconductor device of claim 2, wherein conduction in said channel can be continuously and dynamically varied between a negative differential resistance mode and a non-negative differential resistance mode.

4. The silicon based semiconductor device of claim 1, wherein said trapping region is configured such that said charge carriers are trapped only temporarily and such that a continuous trapping and de-trapping mechanism is set up between said trapping layer and said channel.

5. The silicon based semiconductor device of claim 1, wherein a threshold voltage of the silicon based semiconductor device is controlled by said drain bias voltage.

6. The silicon based semiconductor device of claim I wherein an amount of charge carriers trapped by the charge trapping region is controlled by said drain bias voltage.

7. A metal-insulator-semiconductor field-effect transistor (MISFET) comprising: first conductivity type doped source and drain regions formed in the surface of a semiconductor substrate and separated by a second conductivity type doped channel region, said second conductivity type being opposite to said first conductivity; a gate formed over and electrically insulated from said channel region by a gate dielectric, which gate dielectric includes a charge trapping layer; said charge trapping layer being located near an interface with said second conductivity type channel region and being configured to trap charge and cause a threshold voltage of the MISFET to be significantly altered in a dynamic and reversible manner in response to an adjustable bias voltage applied to the MISFET; wherein said adjustable bias voltage is not a program and/or an erase cycle.

8. The MISFET of claim 7 wherein a negative differential resistance characteristic is achieved by rapid trapping and de-trapping of electrons to and from said charge trapping sites in said charge trapping layer.

9. The MISFET of claim 7 wherein said charge trapping layer includes charge-trapping sites consisting of one or more islands of metal or semiconductor embedded in said gate dielectric.

10. The MISFET of claim 7 wherein said charge trapping layer comprises silicon nitride.

11. The MISFET of claim 7, wherein said adjustable bias voltage is applied to said first conductivity type source and drain regions.

12. The MISFET of claim 7, wherein a trapping mechanism by said charge trapping layer can be selectively disabled by applying a separate bias voltage to a body region portion of the MISFET.

Brief Patent Description - Full Patent Description - Patent Claims

Click on the above for other options relating to this Charge trapping device patent application.
###

How KEYWORD MONITOR works... a FREE service from FreshPatents
1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored.
3. Each week you receive an email with patent applications related to your keywords.
Start now! - Receive info on patent apps like Charge trapping device or other areas of interest.
###

Previous Patent Application:
Abrupt channel doping profile for fermi threshold field effect transistors
Next Patent Application:
Double gate strained-semiconductor-on-insulator device structures
Industry Class:
Active solid-state devices (e.g., transistors, solid-state diodes)

###

Design/code © 2009 FreshContext LLC/Freshpatents.com. Website Terms and Conditions - Also read: About this Page
Patent data source: patents published by the United States Patent and Trademark Office (USPTO)
Information published here is for research/educational purposes only (and in conjunction with our Keyword Monitor) and is not meant to be used in place of the full USPTO patent document/images or a comprehensive patent archive search. Complete official applications are on file at the USPTO and often contain additional data/images (Freshpatents is currently text-only). FreshPatents.com is not affiliated with or endorsed by the USPTO or firms/individuals or products/designs/ideas related to listed patents.

FreshPatents.com Support
Thank you for viewing the Charge trapping device patent info.
IP-related news and info

Results in 0.1446 seconds

Other interesting Feshpatents.com categories:
Computers: Graphics , I/O , Processors , Dyn. Storage , Static Storage , Printers 174

* Protect your Inventions
* US Patent Office filing

Provisional Patent
Utility Patent

PATENT INFO