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Charge trapping deviceRelated Patent Categories: Active Solid-state Devices (e.g., Transistors, Solid-state Diodes), Field Effect Device, Having Insulated Electrode (e.g., Mosfet, Mos Diode)Charge trapping device description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20060197122, Charge trapping device. Brief Patent Description - Full Patent Description - Patent Application Claims
RELATED APPLICATIONS [0001] The present invention claims priority to and is a continuation of an application titled "CHARGE TRAPPING DEVICE" Ser. No. 10/753,948 filed Jan. 7, 2004 which claims priority to and is a continuation of an application titled "CHARGE TRAPPING DEVICE AND METHOD FOR IMPLEMENTING A TRANSISTOR HAVING A CONFIGURABLE THRESHOLD" Ser. No. 10/252,906 filed Sep. 23, 2002. [0002] The aforementioned Ser. No. 10/252,906 application claims priority to and is in turn a continuation of an application titled "CHARGE TRAPPING DEVICE AND METHOD FOR IMPLEMENTING A TRANSISTOR HAVING A NEGATIVE DIFFERENTIAL RESISTANCE MODE" (Ser. No. 09/603,102 filed Jun. 22, 2000, now U.S. Pat. No. 6,479,862), and is farther related to and claims priority to the following applications: an application titled "CMOS PROCESS COMPATIBLE, TUNABLE NDR (NEGATIVE DIFFERENTIAL RESISTANCE) DEVICE AND METHOD OF OPERATING SAME," (Ser. No. 09/603,101 filed Jun. 22, 2000, now U.S. Pat. 6,512,274); and an application titled "CMOS COMPATIBLE PROCESS FOR MAKING A TUNABLE NEGATIVE DIFFERENTIAL RESISTANCE (NDR) DEVICE"(Ser. No. 09/602,658 filed Jun. 22, 2000, now U.S. Pat. No. 6,596,617). [0003] The above materials are expressly incorporated by reference herein. FIELD OF THE INVENTION [0004] This invention relates to semiconductor devices and more particularly to a structures and devices that enable a transistor to operate with a negative differential resistance mode. The present invention is applicable to a wide range of semiconductor integrated circuits, particularly for high-density memory and logic applications, as well as power management. BACKGROUND OF THE INVENTION [0005] Devices that exhibit a negative differential resistance (NDR) characteristic, such that two stable voltage states exist for a given current level, have long been sought after in the history of semiconductor-devices. When Nobel Prize winner Leo Esaki discovered the NDR characteristic in a resonant tunneling diode (RTD), the industry looked expectantly to the implementation of faster and more efficient circuits using these devices. NDR based devices and principles are discussed in a number of references, including the following that are hereby incorporated by reference and identified by bracketed numbers [ ] where appropriate below: [0006] [1] P. Mazumder, S. Kulkami, M. Bhattacharya, J. P. Sun and G. I. Haddad, "Digital Circuit Applications of Resonant Tunneling Devices," Proceedings of the IEEE, Vol. 86, No. 4, pp. 664-686, 1998. [0007] [2] W. Takao, U.S. Pat. No. 5,773,996, "Multiple-valued logic circuit" (issued Jun. 30, 1998) [0008] [3] Y. Nakasha and Y. Watanabe, U.S. Pat. No. 5,390,145, "Resonance tunnel diode memory" (issued Feb. 14, 1995) [0009] [4] J. P. A. Van Der Wagt, "Tunneling-Based SRAM," Proceedings of the IEEE, Vol. 87, No. 4, pp. 571-595, 1999. [0010] [5] R. H. Mathews, J. P. Sage, T. C. L. G. Sollner, S. D. Calawa, C.-L. Chen, L. J. Mahoney, P. A. Maki and K. M Molvar, "A New RTD-FET Logic Family," Proceedings of the IEEE, Vol. 87, No. 4, pp. 596-605, 1999. [0011] [6] H. J. De Los Santos, U.S. Pat. No. 5,883,549, "Bipolar junction transistor (BJT)-resonant tunneling diode (RTD) oscillator circuit and method (issued Mar. 16, 1999) [0012] [7] S. L. Rommel, T. E. Dillon, M. W. Dashiell, H. Feng, J. Kolodzey, P. R. Berger, P. E. Thompson, K. D. Hobart, R. Lake, A. C. Seabaugh, G. Klimeck and D. K. Blanks, "Room temperature operation of epitaxially grown Si/Si.sub.0.5Ge.sub.0.5/Si resonant interband tunneling diodes," Applied Physics Letters, Vol. 73, No. 15, pp. 2191-2193, 1998. [0013] [8] S. J. Koester, K. Ismail, K. Y. Lee and J. O. Chu, "Negative differential conductance in lateral double-barrier transistors fabricated in strained Si quantum wells," Applied Physics Letters, Vol. 70, No. 18, pp. 2422-2424, 1997. [0014] [9] G. I. Haddad, U. K. Reddy, J. P. Sun and R. K. Mains, "The bound-state resonant tunneling transistor (BSRTT): Fabrication, d.c. I-V characteristics, and high-frequency properties," Superlattices and Microstructures, Vol. 7, No. 4, p. 369, 1990. [0015] [10] Kulkarni et. al., U.S. Pat. No. 5,903,170, "Digital Logic Design Using Negative Differential Resistance Diodes and Field-Effect Transistors (issued May 11, 1999). [0016] A wide range of circuit applications for NDR devices are proposed in the above references, including multi-valued logic circuits [1,2], static memory (SRAM) cells [3,4], latches [5], and oscillators [6]. To date, technological obstacles have hindered the widespread use of RTD devices in conventional silicon-based integrated circuits (ICs), however. [0017] The most significant obstacle to large-scale commercialization has been the technological challenge of integrating high-performance NDR devices into a conventional IC fabrication process. The majority of RTD-based circuits require the use of transistors, so the monolithic integration of NDR devices with predominant complementary metal-oxide-semiconductor (CMOS) transistors is the ultimate goal for boosting circuit functionality and/or speed. Clearly, the development of a CMOS-compatible NDR device technology would constitute a break-through advancement in silicon-based IC technology. The integration of NDR devices with CMOS devices would provide a number of benefits including at least the following for logic and memory circuits: [0018] 1) reduced circuit complexity for implementing a given function; [0019] 2) lower-power operation; and [0020] 3) higher-speed operation. [0021] Significant manufacturing cost savings could he achieved concomitantly, because more chips could be fabricated on a single silicon wafer without a significant increase in wafer-processing cost. Furthermore, a CMOS compatible NDR device could also be greatly utilized in power management circuitry for ICs, which is an area of growing importance due to the proliferation of portable electronic devices (PDAS, cell phones, etc.) [0022] A tremendous amount of effort has been expended over the past several decades to research and develop silicon-based NDR devices in order to achieve compatibility with mainstream CMOS technology, because of the promise such devices hold for increasing IC performance and functionality. Efforts thus far have only yielded quantum-mechanical-tunneling-based devices that require either prohibitively expensive process technology or extremely low operating temperatures which are impractical for high-volume applications. One such example in the prior art requires deposition of alternating layers of silicon and silicon-germanium alloy materials using molecular beam epitaxy (MBE) to achieve monolayer precision to fabricate the NDR device [7]. MBE is an expensive process which cannot be practically employed for high-volume production of semiconductor devices. Another example in the prior art requires the operation of a device at extremely low temperatures (1.4 K) in order to achieve significant NDR characteristics [8]. This is impractical to implement for high-volume consumer electronics applications. [0023] A further drawback of the tunnel diode is that it is inherently a two-terminal device. Three (or more) terminal devices are preferred as switching devices, because they allow for the conductivity between two terminals to be controlled by a voltage or current applied to a third terminal, an attractive feature for circuit design as it allows an extra degree of freedom and control in circuit designs. Three-terminal quantum devices which exhibit NDR characteristics such as the resonant tunneling transistor (RTT) [9] have been demonstrated; the performance of these devices has also been limited due to difficulties in fabrication, however. Some bipolar devices (such as SCRs) also can exhibit an NDR effect, but this is limited to embodiments where the effect is achieved with two different current levels. In other words, the I-V curve of this type of device is not extremely useful because it does not have two stable voltage states for a given current. [0024] Accordingly, there exists a significant need for a new three-terminal NDR device which can be easily and reliably implemented in a conventional CMOS technology. In addition, it is further desirable that such a three-terminal device can be operated at room temperature. Continue reading about Charge trapping device... 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