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Characterization and verification for integrated circuit designsRelated Patent Categories: Data Processing: Design And Analysis Of Circuit Or Semiconductor Mask, Circuit Design, Testing Or EvaluatingCharacterization and verification for integrated circuit designs description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070157139, Characterization and verification for integrated circuit designs. Brief Patent Description - Full Patent Description - Patent Application Claims
[0001] This application is a continuation in part of, and claims the benefit of priority of, U.S. patent application Ser. Nos. 10/165,214, 10/164,844, 10/164,847, and 10/164,842, all filed Jun. 7, 2002, and Ser. No. 10/200,660, filed Jul. 22, 2002, all assigned to the same assignee as this patent application. The contents of those patent applications are incorporated by reference here. BACKGROUND [0002] This description relates to lithography mask creation for integrated circuits (ICs). [0003] Lithography mask creation and printing assume that projection is done on a film, within a predetermined depth of focus range. However pattern dependencies between the process by which the ICs are fabricated and the pattern that is being created often cause processed films to have significant variation in thickness across a surface, resulting in variation in feature dimensions (e.g. line widths) of integrated circuits (ICs) that are patterned using the mask. As successive non-conformal layers are deposited and polished, the variation becomes worse. Because interconnect lines and connections on higher layers carry power to portions of the chip, the variations can increase the sheet resistance and thus affect the power effectiveness of the chip. [0004] One way to reduce the variations in fabricated chips is to make physical measurements on manufactured wafers containing initial designs of devices and use these measurements to adjust the mask design. Other methods to reduce variation include optical proximity correction (OPC) where subwavelength distortions due to patterned features are identified and corrected. SUMMARY [0005] In general, in one aspect, the invention features a method that includes characterizing variations in feature dimensions of an integrated circuit that is to be fabricated ill accordance with a design by a process that produces topographical variation in the integrated circuit, the variations in feature dimension being caused by the topographical variations. The process that produces topographical variation comprises electroplated copper deposition or chemical mechanical polishing. The process includes a lithographic or etching process that interacts with the topographical variation to produce the variations in feature dimensions. The etching process comprises a plasma etching process. [0006] In general, in another aspect, the invention features a method that includes using a pattern-dependent model of topographical variation to predict feature dimension variations or electrical characteristics of an integrated circuit that is to be fabricated in accordance with a design by a process that produces topological variation, and verifying that the predicted feature dimensions or electrical characteristics conform to the design. [0007] In general, in another aspect, the invention features a method that includes using a pattern-dependent model of topographical variation to predict characteristics of an integrated circuit that is to be fabricated in accordance with a design by a process that includes lithography or etch, and verifying that the predicted characteristics conform to the design, the characteristics including feature dimensions or electrical characteristics. [0008] Implementations of the invention may include one or more of the following features. The process includes plasma etch and the characteristics include sidewall angle, trench width, or trench depth. The characteristics include feature dimensions. The characteristics include electrical characteristics. The process includes electroplated copper deposition. The process includes chemical mechanical polishing. The characteristics comprise feature width. The characteristics are associated with all of the integrated circuit. The characteristics are associated with less than all of the integrated circuit. The verifying of the predicted characteristics includes verifying feature widths. The verifying of the predicted characteristics also includes verifying the topographical variation. The verifying of the predicted characteristics includes verifying physical and electrical parameters that result from feature width variation. The prediction or verification is done in response to a request received electronically from a network. The prediction or verification is provided as a web service. Using a pattern-dependent model of topographical variation to predict characteristics of the integrated circuit includes using the model with respect to at least two different process features. The process features comprise process recipes. The process recipes include different tool settings for a tool. The process recipes include power settings. The process recipes include etch times. The process recipes include polish times. The process recipes include deposition times. The process recipes include pressures. The process features comprise tools. The tools comprise tools made by two different vendors. The process features comprise consumables. The consumables compose photoresists or mask types. The choosing among the process features is based on the predictions. The characterizing is provided as a service in a network. The network comprises an intranet, an extranet, or an internet, and the characterizing is provided in response to user requests. An electronics design automation (EDA) tool in conjunction with the,characterizing. [0009] In general, in another aspect, the invention features a method comprising using a pattern-dependent model to predict variations in feature dimensions of an integrated circuit that is to be fabricated in accordance with a design by a process that includes a fabrication process that will impart topographical variation to the integrated circuit. [0010] Implementations of the invention may include one or more of the following features. The fabrication process comprises electroplated copper deposition (ECD). The fabrication process comprises chemical mechanical polishing (CMP). The model predicts variations in feature dimension resulting from interaction between the fabrication process and a lithography or etch process. The predicting is, provided as a service in a network. The network comprises an intranet, an extranet, or an internet, and the predicting is provided in response to user requests. An electronics design automation (EDA) tool is used in conjunction with the predicting. [0011] In general, in another aspect, the invention features a method comprising using a pattern-dependent model to predict feature dimension characteristics of a level of an integrated circuit that is to be fabricated in accordance with a design, and certifying that the predicted feature dimension characteristics meet specifications of the design. [0012] Implementations of the invention may include one or more of the following features. A circuit component is added to the design after the feature dimension characteristics are predicted, and, after the component is added to the design, the predicted feature dimension characteristics are certified to meet the design specifications. The dimension comprises feature width. The predicting and certifying are provided as a service in a network. The network comprises an intranet, an extranet, or an internet, and the predicting and certifying are provided in response to user requests. An electronics design automation (EDA) tool is used in conjunction with the predicting and the certifying. [0013] In general, in another aspect, the invention features a method comprising using a pattern-dependent model to predict characteristics of an i that is to be fabricated in accordance with a design by a process that includes (a) a fabrication process that will impart topographical variation to the integrated circuit and (b) a lithography or etch process, and certifying that the predicted characteristics meet specifications of the design. [0014] In general, in another aspect, the invention features a method comprising using a pattern-dependent model to predict characteristics of an integrated circuit that is to be fabricated in accordance with a design by a process that includes (a) a fabrication process that will impart topographical variation to the integrated circuit and (b) a subsequent lithography or etch process, and certifying that the predicted characteristics resulting from the process up to the lithography or etch process will meet specifications of the design. [0015] In general, in another aspect, the invention features a method comprising applying a lithographic or etching process to a test wafer, deriving, from the processed test wafer, characterization information about variations of feature dimensions resulting from the lithographic or etching process, and using the characterization information in a pattern-dependent model of the lithographic or etching process. [0016] In general, in another aspect, the invention features a method comprising using a pattern-dependent model to predict relative variations of feature dimensions of an integrated circuit that is to be fabricated in accordance with a design by processes that respectively include different lithographic or etching tools or consumables, and selecting one of the processes for use in fabricating the integrated circuit based on the relative predicted variations. [0017] Implementations of the invention may include one or more of the following features. The predicting is provided as a service in a network. The network comprises an intranet, an extranet, or an internet, and the predicting is provided in response to user requests. An electronics design automation (EDA) tool is used in conjunction with the predicting. The lithography comprises deep ultra-violet (DUV), extremely short UV (EUV), or ion projection lithography (IPL). The feature dimensions are measured by scanning electron microscopy (SEM), scatterometry and scanning probe microscopy, line edge roughness (LER) tools, or three-dimensional measurement techniques. [0018] In general, in another aspect, the invention features a method comprising using a pattern-dependent model to verify that chip-level features of a design of an integrated circuit can be manufactured within focus limitations of a lithographic tool. [0019] Implementations of the invention may include one or more of the following features. The verifying is provided as a service in a network. The network comprises an intranet, an extranet, or an internet, and the verifying is provided in response to user requests. The using an electronics design automation (EDA) tool in conjunction with the verifying. [0020] In general, in another aspect, the invention features a method comprising using a pattern-dependent model to predict whether a design of a level of an integrated circuit can be lithographically imaged in accordance with the design, and if not, adjusting the design or processing parameters so that it can be. [0021] Implementations of the invention may include one or more of the following features. The adjusting includes selecting optimal tool settings of a lithography tool. The adjusting includes selecting optimal photoresist materials. The adjusting includes selecting optimal photoresist deposition recipes. The adjusting includes adjusting tool settings for a tool. The adjusting includes adjusting power settings. The adjusting includes adjusting etch times. The adjusting includes adjusting polish times. The adjusting includes adjusting deposition times. The adjusting includes adjusting include pressures. [0022] Other advantages and features of the invention will become apparent from the following description and from the claims. Continue reading about Characterization and verification for integrated circuit designs... Full patent description for Characterization and verification for integrated circuit designs Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Characterization and verification for integrated circuit designs patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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