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Cathy May patents

Recent bibliographic sampling of Cathy May patents listed/published in the public domain by the USPTO (USPTO Patent Application #,Title):



04/24/14 - 20140115590 - Method and apparatus for conditional transaction abort and precise abort handling
A method for executing a transaction in a data processing system initiates the transaction by a transactional-memory system coupled to that memory component. The method includes initiating the transaction by a transactional-memory system that is part of a memory component of the data processing system. The transaction includes instructions for...
Inventors: Robert J Blainey, Harold W Cain, Iii, Bradly G Frey, Hung Q Le, Cathy May (International Business Machines Corporation)

03/20/14 - 20140081936 - Method and apparatus for recording and profiling transaction failure source addresses in hardware transactional memories
A method for recording and profiling information of a plurality of aborted transactions from a plurality of transactions is executed by processor core with a transactional memory, a transaction failure instruction address register (TFIAR), and a transaction failure data address register (TFDAR). The transactional memory stores information of a plurality...
Inventors: Robert J. Blainey, Harold W. Cain, Susan E. Eisen, Bradley G. Frey, Charles B. Hall, Hung Q. Le, Cathy May (International Business Machines Corporation)

03/13/14 - 20140075441 - Method and apparatus for recording and profiling transaction failure source addresses in hardware transactional memories
A processor core includes a transactional memory, a transaction failure instruction address register (TFIAR), and a transaction failure data address register (TFDAR). The transactional memory stores information of a plurality of transactions executed by the processor core. The processor core retrieves instruction and data address associated with the aborted transaction...
Inventors: Robert J. Blainey, Harold W. Cain, Susan E. Eisen, Bradly G. Frey, Charles B. Hall, Hung Q. Le, Cathy May (International Business Machines Corporation)

03/13/14 - 20140075132 - Method and apparatus for determining failure context in hardware transactional memories
A method for diagnosing an aborted transaction from a plurality of transactions is executed by a processor core with a transactional memory, that stores information corresponding to a plurality of transactions executed by the processor core, and a transaction diagnostic register. The processor core retrieves context summary information from at...
Inventors: Harold W. Cain, Bradley G. Frey, Hung Q. Le, Cathy May

03/13/14 - 20140075131 - Method and apparatus for determining failure context in hardware transactional memories
A processor core includes a transactional memory that stores information corresponding to a plurality of transactions executed by the processor core, and a transaction diagnostic register. The processor core retrieves context summary information from at least one register of the processor core. The processor core stores the context summary information...
Inventors: Harold W. Cain, Bradley G. Frey, Hung Q. Le, Cathy May (International Business Machines Corporation)

02/13/14 - 20140047205 - Interaction of transactional storage accesses with other atomic semantics
In a processor, an instruction sequence including, in order, a load-and-reserve instruction specifying a read access to a target memory block, an instruction delimiting transactional memory access instructions belonging to a memory transaction, and a store-conditional instruction specifying a conditional write access to the target memory block is detected. In...
Inventors: Bradly G. Frey, Guy L. Guthrie, Cathy May, Derek E. Williams (International Business Machines Corporation)

02/13/14 - 20140047196 - Transaction check instruction for memory transactions
A processing unit of a data processing system having a shared memory system executes a memory transaction including a transactional store instruction that causes a processing unit of the data processing system to make a conditional update to a target memory block of the shared memory system conditioned on successful...
Inventors: Bradly G. Frey, Guy L. Guthrie, Cathy May, Derek E. Williams (International Business Machines Corporation)

02/13/14 - 20140047195 - Transaction check instruction for memory transactions
A processing unit of a data processing system having a shared memory system executes a memory transaction including a transactional store instruction that causes a processing unit of the data processing system to make a conditional update to a target memory block of the shared memory system conditioned on successful...
Inventors: Bradly G. Frey, Guy L. Guthrie, Cathy May, Derek E. Williams (International Business Machines Corporation)

02/06/14 - 20140040557 - Nested rewind only and non rewind only transactions in a data processing system supporting transactional storage accesses
In a multiprocessor data processing system having a distributed shared memory system, first and second nested memory transactions are executed, where the first memory transaction is a rewind-only transaction (ROT) and the second memory transaction is a non-ROT memory transaction. The first memory transaction has a transaction body including the...
Inventors: Bradly G. Frey, Guy L. Guthrie, Cathy May, Derek E. Williams (International Business Machines Corporation)

02/06/14 - 20140040551 - Rewind only transactions in a data processing system supporting transactional storage accesses
In a multiprocessor data processing system having a distributed shared memory system, a memory transaction that is a rewind-only transaction (ROT) and that includes one or more transactional memory access instructions and a transactional abort instruction is executed. In response to execution of the one or more transactional memory access...
Inventors: Robert J. Blainey, Bradly G. Frey, Guy L. Guthrie, Cathy May, Derek E. Williams (International Business Machines Corporation)

01/09/14 - 20140013060 - Ensuring causality of transactional storage accesses interacting with non-transactional storage accesses
A data processing system implements a weak consistency memory model for a distributed shared memory system. The data processing system concurrently executes, on a plurality of processor cores, one or more transactional memory instructions within a memory transaction and one or more non-transactional memory instructions. The one or more non-transactional...
Inventors: Bradly G. Frey, Cathy May, Derek E. Williams (International Business Machines Corporation)

01/09/14 - 20140013055 - Ensuring causality of transactional storage accesses interacting with non-transactional storage accesses
A data processing system implements a weak consistency memory model for a distributed shared memory system. The data processing system concurrently executes, on a plurality of processor cores, one or more transactional memory instructions within a memory transaction and one or more non-transactional memory instructions. The one or more non-transactional...
Inventors: Bradly G. Frey, Cathy May, Derek E. Williams (International Business Machines Corporation)

09/27/12 - 20120246658 - Transactional memory preemption mechanism
Mechanisms for executing a transaction in the data processing system are provided. A transaction checkpoint data structure is generated in internal registers of a processor. The transaction checkpoint data structure stores transaction checkpoint data representing a state of program registers at a time prior to execution of a corresponding transaction....
Inventors: Richard L. Arndt, Harold W. Cain, Iii, Bradly G. Frey, Cathy May (International Business Machines Corporation)

07/19/12 - 20120185678 - Hardware thread disable with status indicating safe shared resource condition
A technique for indicating a safe shared resource condition with respect to a disabled thread provides a mechanism for providing a fast indication to other hardware threads that a temporarily disabled thread can no longer impact shared resources, such as shared special-purpose registers and translation look-aside buffers within the processor...
Inventors: Becky Bruce, Giles R. Frazier, Bradly G. Frey, Kumar K. Gala, Cathy May, Michael D. Snyder, Gary Whisenhunt, James Xenidis (International Business Machines Corporation)

04/05/12 - 20120084477 - Transactional memory preemption mechanism
Mechanisms for executing a transaction in the data processing system are provided. A transaction checkpoint data structure is generated in internal registers of a processor. The transaction checkpoint data structure stores transaction checkpoint data representing a state of program registers at a time prior to execution of a corresponding transaction....
Inventors: Richard L. Arndt, Harold W. Cain, Iii, Bradly G. Frey, Cathy May (International Business Machines Corporation)

12/01/11 - 20110296148 - Transactional memory system supporting unbroken suspended execution
Mechanisms are provided, in a data processing system having a processor and a transactional memory, for executing a transaction in the data processing system. These mechanisms execute a transaction comprising one or more instructions that modify at least a portion of the transactional memory. The transaction is suspended in response...
Inventors: Harold W. Cain, Iii, Bradly G. Frey, Benjamin Herrenschmidt, Hung Q. Le, Cathy May, Maged M. Michael, Jose E. Moreira, Priya A. Nagpurkar, Naresh Nayar, Randal C. Swanberg (International Business Machines Corporation)

08/25/11 - 20110208949 - Hardware thread disable with status indicating safe shared resource condition
A technique for indicating a safe shared resource condition with respect to a disabled thread provides a mechanism for providing a fast indication to other hardware threads that a temporarily disabled thread can no longer impact shared resources, such as shared special-purpose registers and translation look-aside buffers within the processor...
Inventors: Becky Bruce, Giles R. Frazier, Bradly G. Frey, Kumar K. Gala, Cathy May, Michael D. Snyder, Gary Whisenhunt, James Xenidis (International Business Machines Corporation)

10/21/10 - 20100268886 - Specifying an access hint for prefetching partial cache block data in a cache hierarchy
A system and method for specifying an access hint for prefetching only a subsection of cache block data, for more efficient system interconnect usage by the processor core. A processing unit receives a data cache block touch (DCBT) instruction containing an access hint and identifying a specific size portion of...
Inventors: Bradly George Frey, Guy Lynn Guthrie, Cathy May, Ramakrishnan Rajamony, Balaram Sinharoy, William John Starke, Peter Kenneth Szwed (International Buisness Machines Corporation)

10/21/10 - 20100268885 - Specifying an access hint for prefetching limited use data in a cache hierarchy
A system and method for specifying an access hint for prefetching limited use data. A processing unit receives a data cache block touch (DCBT) instruction having an access hint indicating to the processing unit that a program executing on the data processing system may soon access a cache block addressed...
Inventors: Bradly G. Frey, Guy L. Guthrie, Cathy May, Balaram Sinharoy, Peter K. Szwed (International Business Machines Corporation)

International Business Machines Corporation, International Buisness Machines Corporation

Archived*
(*May have duplicates - we are upgrading our archive.)

20120246658 - Transactional memory preemption mechanism


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The bibliographic references displayed about Cathy May's patents are for a recent sample of Cathy May's publicly published patent applications. The inventor/author may have additional bibliographic citations listed at the USPTO.gov. FreshPatents.com is not associated or affiliated in any way with the author/inventor or the United States Patent/Trademark Office but is providing this non-comprehensive sample listing for educational and research purposes using public bibliographic data published and disseminated from the United States Patent/Trademark Office public datafeed. This information is also available for free on the USPTO.gov website. If Cathy May filed recent patent applications under another name, spelling or location then those applications could be listed on an alternate page. If no bibliographic references are listed here, it is possible there are no recent filings or there is a technical issue with the listing--in that case, we recommend doing a search on the USPTO.gov website.

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