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  Carburized silicon gate insulators for integrated circuitsUSPTO Application #: 20060017095Title: Carburized silicon gate insulators for integrated circuits Abstract: Silicon carbide films are grown by carburization of silicon to form insulative films. In one embodiment, the film is used to provide a gate insulator for a field effect transistor. The film is grown in a microwave-plasma-enhanced chemical vapor deposition (MPECVD) system. A silicon substrate is first etched in dilute HF solution and rinsed. The substrate is then placed in a reactor chamber of the MPECVD system in hydrogen along with a carbon containing gas. The substrate is then inserted into a microwave generated plasma for a desired time to grow the film. The microwave power varies depending on substrate size. The growth of the film may be continued following formation of an initial film via the above process by using a standard CVD deposition of amorphous SiC. The film may be used to form gate insulators for FET transistors in DRAM devices and flash type memories. It may be formed as dielectric layers in capacitors in the same manner. (end of abstract) Agent: Schwegman, Lundberg, Woessner & Kluth, P.A. - Minneapolis, MN, US Inventors: Leonard Forbes, Kie Y. Ahn USPTO Applicaton #: 20060017095 - Class: 257315000 (USPTO) Related Patent Categories: Active Solid-state Devices (e.g., Transistors, Solid-state Diodes), Field Effect Device, Having Insulated Electrode (e.g., Mosfet, Mos Diode), Variable Threshold (e.g., Floating Gate Memory Device), With Floating Gate Electrode The Patent Description & Claims data below is from USPTO Patent Application 20060017095. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS-REFERENCE TO RELATED APPLICATION [0001] The present application is a continuation of U.S. Ser. No. 08/903,453, filed on Jul. 29, 1997, which is herein incorporated by reference in its entirety. FIELD OF THE INVENTION [0002] The present invention relates to semiconductor field effect transistors, and in particular to insulators for gates of field effect transistors. BACKGROUND OF THE INVENTION [0003] Field-effect transistors (FETs) are typically produced using a standard complementary metal-oxide-semiconductor (CMOS) integrated circuit fabrication process. As is well known in the art, such a process allows a high degree of integration such that a high circuit density can be obtained with the use of relatively few well-established masking and processing steps. A standard CMOS process is typically used to fabricate FETs that each have a gate electrode that is composed of n-type conductively doped polycrystalline silicon (polysilicon) material or other conductive materials. [0004] Field effect transistors (FETs) are used in many different types of memory devices, including EPROM, EEPROM, EAPROM, DRAM and flash memory devices. They are used as both access transistors, and as memory elements in flash memory devices. In these applications, the gate is electrically isolated from other conductive areas of the transistor by an oxide layer. A drawback with FETs having grown oxide insulators is manifested in the use of Fowler-Nordheim tunneling to implement nonvolatile storage devices, such as in electrically erasable and programmable read only memories (EEPROMs). EEPROM memory cells typically use CMOS floating gate FETs. A floating gate FET typically includes a floating (electrically isolated) gate that controls conduction between source and drain regions of the FET. In such memory cells, data is represented by charge stored on the floating gates. Fowler-Nordheim tunneling is one method that is used to store charge on the floating gates during a write operation and to remove charge from the polysilicon floating gate during an erase operation. The high tunneling voltage of grown oxides used to provide such isolation increases the time needed to store charge on the floating gates during the write operation and the time needed to remove charge from the polysilicon floating gate during the erase operation. This is particularly problematic for "flash" EEPROMs, which have an architecture that allows the simultaneous erasure of many floating gate transistor memory cells. Since more charge must be removed from the many floating gates in a flash EEPROM, even longer erasure times are needed to accomplish this simultaneous erasure. There is a need in the art to obtain floating gate transistors allowing faster storage and erasure, such as for use in flash EEPROMs. [0005] Many gate insulators have been tried, such as grown oxides, CVD (chemical vapor deposition) oxides, and deposited layers of silicon nitride, aluminum oxide, tantalum oxide, and titanium oxide with or without grown oxides underneath. The only commonly used gate insulator at the present time is thermally grown silicon oxide. If other insulators are deposited directly on the silicon, high surface state densities result. Composite layers of different insulators are first grown and then deposited, such as oxide-CVD oxide or oxide-CVD nitride combinations. If composite insulators are used, charging at the interface between the insulators results due to trap states at this interface, a bandgap discontinuity, and/or differences in conductivity of the films. [0006] There is a need for a gate insulator which provides a low tunneling barrier. There is a further need to reduce the tunneling time to speed up storage and retrieval of data in memory devices. There is yet a further need for a gate insulator with less charging at the interface between composite insulator layers. A further need exists to form gate insulators with low surface state densities. SUMMARY OF THE INVENTION [0007] Silicon carbide films are grown by carburization of silicon to form insulative films. In one embodiment, the film is used to provide a gate insulator for a field effect transistor. The film is grown in a microwave-plasma-enhanced chemical vapor deposition (MPECVD) system. A silicon substrate is first etched in dilute HF solution and rinsed. The substrate is then placed in a reactor chamber of the MPECVD system in hydrogen along with a carbon containing gas. The substrate is then inserted into a microwave generated plasma for a desired time to grow the film. The microwave power varies depending on substrate size. [0008] The resulting SiC film is preferably amorphous and has low surface state densities. It provides a gate insulator having a much lower tunneling barrier as compared to grown oxides which are widely used today. The lower tunneling barrier results in reduced tunneling times and allows reduction of power supply voltages. Further, charging at interfaces between composite insulators is reduced. [0009] Methane, and other carbon containing gases having from about one to ten carbon atoms per molecule may be used. The temperature of the system may vary between approximately 915 degrees C. to 1250 degrees C., with films growing faster at higher temperatures. Thicknesses of the resulting film range from 2 nm in a time period as short as 3 minutes, to as thick as 4500 Angstrom in one hour. The thicker films require longer time and higher temperature since the formation of SiC is a diffusion limited process. [0010] The growth of the film may be continued following formation of an initial film via the above process by using a standard CVD deposition of amorphous SiC to form a composite insulator. The film may be used to form gate insulators for flash type memories as well as gate insulators for CMOS and MOS transistors used in semiconductors such as DRAMs. Further, since SiC has a fairly high dielectric constant, it may be formed as dielectric layers in capacitors in the same manner. It can also be used to form gate insulators for photo sensitive FETs for imaging arrays. BRIEF DESCRIPTION OF THE DRAWINGS [0011] FIG. 1 is a cross-sectional view, illustrating one embodiment of a transistor according to one aspect of the invention, including a grown silicon carbide (SiC) gate insulator. [0012] FIG. 2 is a cross-sectional view, illustrating one embodiment of a transistor according to one aspect of the invention, including a grown silicon carbide (SiC) gate insulator. [0013] FIG. 3 is a cross-sectional view, illustrating one embodiment of a capacitor according to one aspect of the invention, including a grown silicon carbide (SiC) dielectric. [0014] FIG. 4 is a simplified block diagram illustrating generally one embodiment of a memory system incorporating grown SiC gate insulated FETs according to one aspect of the present invention. [0015] FIG. 5 is a simplified block circuit diagram of an imaging device employing photo sensitive transistors having grown SiC gate insulators. DESCRIPTION OF THE EMBODIMENTS [0016] In the following detailed description, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized and that structural, logical and electrical changes may be made without departing from the spirit and scope of the present invention. The terms wafer and substrate used in the following description include any semiconductor-based structure having an exposed surface with which to form the integrated circuit structure of the invention. Wafer and substrate are used interchangeably to refer to semiconductor structures during processing, and may include other layers that have been fabricated thereupon. Both wafer and substrate include doped and undoped semiconductors, epitaxial semiconductor layers supported by a base semiconductor or insulator, as well as other semiconductor structures well known to one skilled in the art. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims. [0017] FIG. 1 is a cross-sectional view illustrating generally, by way of example, one embodiment of a n-channel FET provided by the invention. The FET includes a source region 102, a drain region 104 and a gate region 106. In one embodiment, source 102 and drain 104 are fabricated by forming regions of highly doped (n+) regions in a lightly doped (p-) silicon semiconductor substrate 108. In another embodiment, substrate 108 includes a thin semiconductor surface layer formed on an underlying insulating portion, such as in a SOI or other thin film transistor process technology. Source 102 and drain 104 are separated by a predetermined length in which a channel region 110 is formed. [0018] In one embodiment, for example, layer 112 is a polysilicon control gate in a floating gate transistor in an electrically erasable and programmable read-only memory (EEPROM) memory cell. In this embodiment, gate 106 is floating (electrically isolated) for charge storage thereupon, such as by known EEPROM techniques. In another embodiment, for example, layer 112 is, a metal or other conductive interconnection line that is located above gate 106. Continue reading... Full patent description for Carburized silicon gate insulators for integrated circuits Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Carburized silicon gate insulators for integrated circuits patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Carburized silicon gate insulators for integrated circuits or other areas of interest. ### Previous Patent Application: Method for simultaneously fabricating ono-type memory cell, and gate dielectrics for associated high voltage write transistors and gate dielectrics for low voltage logic transistors by using issg Next Patent Application: Non-volatile memory devices with improved insulation layers and methods of manufacturing such devices Industry Class: Active solid-state devices (e.g., transistors, solid-state diodes) ### FreshPatents.com Support Thank you for viewing the Carburized silicon gate insulators for integrated circuits patent info. IP-related news and info Results in 1.52362 seconds Other interesting Feshpatents.com categories: Computers: Graphics , I/O , Processors , Dyn. Storage , Static Storage , Printers |
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