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06/28/07 - USPTO Class 228 |  102 views | #20070145097 | Prev - Next | About this Page  228 rss/xml feed  monitor keywords

Carbon nanotubes solder composite for high performance interconnect

USPTO Application #: 20070145097
Title: Carbon nanotubes solder composite for high performance interconnect
Abstract: An embodiment of the present invention is an interconnect technique. Carbon nanotubes (CNTs) are prepared. A CNT-solder composite paste is formed containing the CNTs and solder with a pre-defined volume fraction. (end of abstract)



Agent: Blakely Sokoloff Taylor & Zafman - Los Angeles, CA, US
Inventor: Daewoong Suh
USPTO Applicaton #: 20070145097 - Class: 228101000 (USPTO)

Related Patent Categories: Metal Fusion Bonding, Process

Carbon nanotubes solder composite for high performance interconnect description/claims


The Patent Description & Claims data below is from USPTO Patent Application 20070145097, Carbon nanotubes solder composite for high performance interconnect.

Brief Patent Description - Full Patent Description - Patent Application Claims
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BACKGROUND

[0001] 1. Field of the Invention

[0002] Embodiments of the invention relate to the field of nanotechnology, and more specifically, to carbon nanotubes.

[0003] 2. Description of Related Art

[0004] Carbon nanotubes (CNTs) are promising elements in nanotechnology. They are fullerene-related structures which consist of graphene cylinders. Applications that may be benefited using carbon nanotubes include high thermal conductivity materials for future packaging thermal demands. The solders used in interconnect between the silicon (Si) die and the substrate have inherently lower resistance to electro-migration primarily due to their electrical resistivity and lower strength or modulus.

[0005] Typical solder has a critical product of electro-migration value approximately 10.sup.2 times lower than copper (Cu), which is used in metallization in silicon die. The critical current density beyond which electro-migration may become a problem is approximately 10.sup.6 A/cm.sup.2 for Cu. Therefore, the critical current density beyond which electro-migration may become a problem is approximately 10.sup.4 A/cm.sup.2 for solder because it is 10.sup.2 times lower than Cu. In other words, the existing solder may face serious electro-migration risk when the current density reaches approximately 10.sup.4 A/cm.sup.2. This current density is being approached by existing technology. Presently, the solder electro-migration is driven by the interfacial reaction and/or defect (e.g., void or trapped filler) not necessarily by the inherent electro-migration in the solder. Although the electro-migration issues may be addressed by other techniques, the solder soon faces electro-migration risk because it starts to be subject to intensive electro-migration damage at current densities around or greater than 10.sup.4 A/cm.sup.2.

BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Embodiments of invention may best be understood by referring to the following description and accompanying drawings that are used to illustrate embodiments of the invention. In the drawings:

[0007] FIG. 1 is a diagram illustrating a system in which one embodiment of the invention may be practiced.

[0008] FIG. 2A is a diagram illustrating a package according to one embodiment of the invention.

[0009] FIG. 2B is a diagram illustrating a solder bump made by a composite paste according to one embodiment of the invention.

[0010] FIG. 3 is a flowchart illustrating a process to form a composite paste according to one embodiment of the invention.

[0011] FIG. 4A is a flowchart illustrating a process to form CNT-solder composite paste using long CNTs according to one embodiment of the invention.

[0012] FIG. 4B is a flowchart illustrating a process to form CNT-solder composite paste using short CNTs according to one embodiment of the invention.

[0013] FIG. 5 is a diagram illustrating resistivity reduction as function of CNT volume fraction according to one embodiment of the invention.

DESCRIPTION

[0014] An embodiment of the present invention is an interconnect technique. Carbon nanotubes (CNTs) are prepared. A CNT-solder composite paste is formed containing the CNTs and solder with a pre-defined volume fraction. The CNT-solder composite paste may then be applied to an interconnect between a die and a substrate.

[0015] In the following description, numerous specific details are set forth. However, it is understood that embodiments of the invention may be practiced without these specific details. In other instances, well-known circuits, structures, and techniques have not been shown to avoid obscuring the understanding of this description.

[0016] One embodiment of the invention may be described as a process which is usually depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe the operations as a sequential process, many of the operations can be performed in parallel or concurrently. In addition, the order of the operations may be re-arranged. A process is terminated when its operations are completed. A process may correspond to a method, a program, a procedure, a method of manufacturing or fabrication, etc.

[0017] An embodiment of the present invention is a technique to form a composite paste for high performance interconnects. The composite paste may be used in any interconnect applications such as die attachment to a package substrate. The composite paste includes carbon nanotubes (CNTs) dispersed within a solder paste with a pre-defined volume fraction. The solder paste includes a mixture of solder powder and a paste ingredient. The CNTs may be metallic single-wall or multi-wall CNTs.

[0018] The CNTs have thermal and electrical properties that are superior to those of metallic materials in several aspects. First, a metallic single-wall or multi-wall CNT is a ballistic conductor, along the tube axis, independent of the tube length. For example, metallic CNTs with lengths of 5-10 .mu.m may have electrical resistivity several times lower that that of copper (Cu) or silver (Ag). Second, CNTs have extraordinary current carrying capability without failure exceeding 10.sup.9 A/cm.sup.2 due to their strong covalent bonding. Experiments show that CNTs may show no degradation at current density of 10.sup.9 A/cm.sup.2 at 250.degree. C. for more than 300 hours. Third, CNTs exhibit very high thermal conductivity of approximately 3,000 W/Km along the tube axis. This thermal conductivity far exceeds the best metallic material such as copper which has a conductivity of only about 420 W/Km, or even diamond with a conductivity of about 2,000 W/Km. By incorporating CNTs in solder paste for use in microelectronic interconnects, the solder technology may be extended beyond the current density of 10.sup.4 A/cm.sup.2. The resulting CNT-solder composite paste provides many advantages. First, CNT serves a high electrical conductance path. Second, electron wind through the solder is reduced due to preferential electrical conductance through the CNTs, resulting in reduced electro-migration damage in the solder. Third, CNTs strengthen the solder matrix, leading to enhanced reliability.

[0019] FIG. 1 is a diagram illustrating a system 100 in which one embodiment of the invention can be practiced. The system 100 includes a wafer fabrication phase 105, wafer preparation phase 110, a wafer dicing phase 120, a composite paste formation phase 125, an encapsulation phase 130, a testing phase 140, and a board assembly phase 150. The system 100 represents a manufacturing flow of a semiconductor packaging process.

[0020] The wafer fabrication phase 105 fabricates the wafer containing a number of dice. The individual dice may be any microelectronic devices such as microprocessors, memory devices, interface circuits, etc. The wafer fabrication phase 105 includes typical processes for semiconductor fabrication such as preparation of the wafer surface, growth of silicon dioxide (SiO.sub.2), patterning and subsequent implantation or diffusion of dopants to obtain the desired electrical properties, growth or deposition of a gate dielectric, and growth or deposition of insulating materials, depositing layers of metal and insulating material and etching it into the desired patterns. Typically the metal layers consist of aluminium or more recently copper. The various metal layers are interconnected by etching holes, called "vias," in the insulating material.

[0021] The wafer preparation phase 110 prepares a wafer containing dice for packaging and testing. During this phase, the wafers are sorted after the patterning process. An inspection may be carried out to check for wafer defects. Then, the wafer may be mounted on a backing tape that adheres to the back of the wafer. The mounting tape provides mechanical support for handling during subsequent phases.

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