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Capacitor fabrication methods and capacitor constructionsRelated Patent Categories: Semiconductor Device Manufacturing: Process, Making Field Effect Device Having Pair Of Active Regions Separated By Gate Structure By Formation Or Alteration Of Semiconductive Active Regions, Having Insulated Gate (e.g., Igfet, Misfet, Mosfet, Etc.), Including Passive Device (e.g., Resistor, Capacitor, Etc.), CapacitorCapacitor fabrication methods and capacitor constructions description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070178640, Capacitor fabrication methods and capacitor constructions. Brief Patent Description - Full Patent Description - Patent Application Claims
TECHNICAL FIELD [0001] The aspects of the invention relate to capacitor fabrication methods including forming conductive barrier layers and capacitor constructions having conductive barrier layers. BACKGROUND OF THE INVENTION [0002] Capacitors are common devices used in electronics, such as integrated circuits, and particularly semiconductor-based technologies. Two common capacitor structures include metal-insulator-metal (MIM) capacitors and metal-insulator-semiconductor (MIS) capacitors. One important factor to consider when selecting a capacitor structure may be the capacitance per unit area. MIS capacitors may be advantageous since a first electrode as the semiconductor may be formed of hemispherical grain (HSG) polysilicon that exhibits a higher surface area in a given region compared to a planar surface of amorphous silicon. The higher surface area provides more capacitance per unit area occupied by a capacitor. [0003] However, a high K factor (also known as dielectric constant or ".kappa.") dielectric material may be desirable to further enhance capacitance. Ta.sub.2O.sub.5 is one example of a high K factor dielectric, but it inherently forms an interfacial dielectric layer of SiO.sub.2 when formed on a capacitor electrode comprising HSG. The interfacial dielectric exhibits a lower K factor than Ta.sub.2O.sub.5 and thus reduces the effective dielectric constant for the capacitor construction. Such reduction may be significant enough to eliminate any gain in capacitance per unit area otherwise achieved by using HSG instead of a planar electrode. Use of other oxygen containing high K dielectric materials has proved to create similar problems. [0004] Because it may be desirable to provide area enhancement of an electrode in a MIM structure using HSG, one attempt at addressing the stated problem is forming a silicon nitride insulative barrier layer over the HSG. The silicon nitride barrier layer may be formed by nitridizing the silicon of the outer surface of HSG. Unfortunately, silicon nitride exhibits a K factor of only about 7, less than the K factor of some high K factor dielectrics that are desirable. Accordingly, even the silicon nitride barrier layer reduces the effective dielectric constant of the capacitor. SUMMARY OF THE INVENTION [0005] In one aspect of the invention, a capacitor fabrication method may include forming a first capacitor electrode over a substrate and atomic layer depositing a conductive barrier layer to oxygen diffusion over the first electrode. A capacitor dielectric layer may be formed over the first electrode and a second capacitor electrode may be formed over the dielectric layer. [0006] Another aspect of the invention may include chemisorbing a layer of a first precursor at least one monolayer thick over the first electrode and chemisorbing a layer of a second precursor at least one monolayer thick on the first precursor layer, a chemisorption product of the first and second precursor layers being comprised by a layer of a conductive barrier material. [0007] Also, in another aspect of the invention a capacitor fabrication method may include forming a first capacitor electrode over a substrate. The first electrode can have an inner surface area per unit area and an outer surface area per unit area that are both greater than an outer surface area per unit area of the substrate. A capacitor dielectric layer may be formed over the first electrode and a second capacitor electrode may be formed over the dielectric layer. [0008] A still further aspect includes a capacitor fabrication method of forming an opening in an insulative layer over a substrate, the opening having sides and a bottom, forming a layer of polysilicon over the sides and bottom of the opening, and removing the polysilicon layer from over the bottom of the opening. At least some of the polysilicon layer may be converted to hemispherical grain polysilicon. A first capacitor electrode may be conformally formed on the converted polysilicon, the first electrode being sufficiently thin that the first electrode has an outer surface area per unit area greater than an outer surface area per unit area of the substrate underlying the first electrode. A capacitor dielectric layer may be formed over the first electrode and a second capacitor electrode may be formed over the dielectric layer. [0009] Other aspects of the invention include the capacitor constructions formed from the above described methods. BRIEF DESCRIPTION OF THE DRAWINGS [0010] Preferred embodiments of the invention are described below with reference to the following accompanying drawings. [0011] FIG. 1 is an enlarged view of a section of a semiconductor wafer at one processing step in accordance with the invention. [0012] FIG. 2 is an enlarged view of the section of the FIG. 1 wafer at a processing step subsequent to that depicted by FIG. 1. [0013] FIG. 3 is an enlarged view of the section of the FIG. 1 wafer at a processing step subsequent to that depicted by FIG. 2. [0014] FIG. 4 is an enlarged view of the section of the FIG. 1 wafer at a processing step subsequent to that depicted by FIG. 3. [0015] FIG. 5 is an enlarged view of the section of the FIG. 1 wafer at a processing step subsequent to that depicted by FIG. 4. [0016] FIG. 6 is an enlarged view of the section of the FIG. 1 wafer at a processing step subsequent to that depicted by FIG. 5. [0017] FIG. 7 is an enlarged view of the section of the FIG. 1 wafer at an alternate embodiment processing step subsequent to that depicted by FIG. 2 in accordance with alternate aspects of the invention. [0018] FIG. 8 is an enlarged view of the section of the FIG. 1 wafer at a processing step subsequent to that depicted by FIG. 7. [0019] FIG. 9 is an enlarged view of the section of the FIG. 1 wafer at a processing step subsequent to that depicted by FIG. 8. [0020] FIG. 10 is an enlarged view of the section of the FIG. 1 wafer at a processing step subsequent to that depicted by FIG. 9. Continue reading about Capacitor fabrication methods and capacitor constructions... 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