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  Canary device for failure analysisUSPTO Application #: 20060195285Title: Canary device for failure analysis Abstract: A diagnostic system and method for testing an integrated circuit (IC) during fabrication thereof, wherein the diagnostic system comprises at least one IC chip comprising an electrical signature; a sacrificial circuit adjacent to the IC chip and comprising a known electrical signature and intentionally mis-designed circuitry; and a comparator adapted to compare the electrical signature of the IC chip with the known electrical signature of the sacrificial circuit, wherein a match in the electrical signature of the IC chip with the known electrical signature of the sacrificial circuit indicates that the IC chip is mis-designed. The diagnostic system further comprises a semiconductor wafer comprising a plurality of IC chips and a kerf area separating one IC chip from another IC chip. The sacrificial circuit is located in the kerf area or alternatively on each of the plurality of IC chips. A mis-designed IC chip comprises abnormally functioning circuitry. (end of abstract)
Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC - Annapolis, MD, US Inventors: Pierre J. Bouchard, Mark C. Hakey, Mark E. Masters, Leah M. Pastel, James A. Slinkman, David P. Vallett USPTO Applicaton #: 20060195285 - Class: 702117000 (USPTO) Related Patent Categories: Data Processing: Measuring, Calibrating, Or Testing, Testing System, Of Circuit The Patent Description & Claims data below is from USPTO Patent Application 20060195285. Brief Patent Description - Full Patent Description - Patent Application Claims
BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The embodiments of the invention generally relate to testing and analyzing microelectronic devices, and more particularly to integrated circuit (IC) diagnostic techniques used during IC fabrication and processing. [0003] 2. Description of the Related Art [0004] Missing, incorrect, or over/under processing of individual manufacturing steps are common problems in the semiconductor industry, especially when new process technologies are under development. Fast discovery of the root cause(s) of these problems and immediate correction is therefore a key to success in this competitive industry. These mis-processed semiconductor steps (for example, missing halo implant) manifest different device performance characteristics, and are often difficult or even impossible to locate with particularity (i.e., pin point) without exhaustive and expensive failure analysis diagnostic techniques and/or time consuming engineering wafer split lot experiments, which ultimately compare electrical performance of intentionally mis-processed to correctly processed wafers. [0005] The areas between the actual chips on a semiconductor wafer that eventually get destroyed during dicing are called "kerfs" or "streets". Typically, semiconductor manufacturers place easily testable circuit and device structures in the area between individual chips on a wafer (i.e., the "kerf"), but usually such structures are robustly designed, and are tailored to device engineering needs. In addition, these kerf structures receive the identical processing as the entire wafer (correctly or incorrectly), since the kerf is intended to supply device and circuit characteristics to predict the actual chip performance and yield. However, currently the kerf is not designed, intended, and is rarely used as a "diagnostic failure analysis" tool. Manufacturers use the kerf area to place numerous circuits for the purpose of testing and monitoring the health of the processing as the wafers go through the line. Many types of transistors, resistors, capacitors, inductors, and logic and analog circuits thereof are configured to measure myriad parameters like sheet resistance, contact resistance, insulator capacitance, threshold voltage, leakage, defect density, line widths, junction depths, etc. These circuits are wired to relatively large metal pads that are probed by testers at various points during manufacture in a process called "inline test." [0006] The monitor circuits above require that the semiconductor processing be of sufficient quality that the monitors themselves are functional, and able to detect more subtle processing errors. In other words, if entire layers are missing, or significantly out of "spec" (specification), then the circuit cannot monitor normal process variations and subtle problems, and diagnosing these gross errors is made even more difficult. [0007] Without the aid of the monitor circuits, the only known methods for diagnosing the gross errors described above are running expensive and time-consuming experiments in an attempt to duplicate the problem under known processing conditions, and expensive "brute-force" laboratory inspection using high-sensitivity instrumentation in a slow and often dead-end "shotgun" approach. [0008] Moreover, with most current failure analysis techniques and available electrical test information, definitive diagnosis typically cannot be achieved without months of long and costly engineering split lot experiments. Moreover, even then, the engineering split lot experiment selection may be incorrect, thereby yielding unusable diagnostic information, thus requiring additional split lots. [0009] U.S. Pat. No. 6,797,981 ("the '981 patent") incorporated herein by reference uses purposely "designed-in" errors to test semiconductor wafers. However these errors are meant to mimic "random" process defects (foreign material, localized extra or missing shapes) that affect only very small and localized areas of a chip and are detectable using known diagnostic methods. The '981 patent is a way to test those known diagnostic methods in a systematic way. However, when entire levels or process steps are missing in a wafer, all known diagnostic methods are generally rendered useless. Hence, there is a need to allow one to diagnose very gross process errors when entire levels or process steps are missing in a wafer and/or the associated circuitry. [0010] Thus, the conventional techniques generally fail to provide an adequate and timely diagnostic failure analysis/technique. Therefore, there remains a need for a novel inexpensive diagnostic technique used in testing an element of a semiconductor manufacturing process. SUMMARY OF THE INVENTION [0011] In view of the foregoing, an embodiment of the invention provides a diagnostic system for testing an integrated circuit (IC) during fabrication of the IC, wherein the diagnostic system comprises at least one principal circuit adjacent to the IC chip comprising an electrical signature; a sacrificial circuit adjacent to the IC chip, wherein the sacrificial circuit comprising a known electrical signature; and a comparator adapted to compare the electrical signature of the principal circuit with the known electrical signature of the sacrificial circuit, wherein upon gross failure of the principal circuit a match in the electrical signature of the principal circuit with the known electrical signature of any of the sacrificial circuits indicates that the IC chip was mis-designed or mis-processed in the same manner as the sacrificial circuit was intentionally mis-designed to be mis-processed. The diagnostic system further comprises a semiconductor wafer comprising a plurality of IC chips and a kerf area separating one IC chip from another IC chip. In one embodiment, the sacrificial circuit is located in the kerf area. In another embodiment, the sacrificial circuit is located on each of the plurality of IC chips. [0012] The sacrificial circuit comprises intentionally mis-designed circuitry comprising a defect, which comprises any of missing interconnect levels, extraneous interconnect levels, missing source/drain implants, off-specification source/drain implants, missing well implants, off-specification well implants, deposition errors, etching errors, off-specification polysilicon gate thicknesses, missing silicide, ill-formed silicide, missing contacts, ill-formed contacts, field oxide variations, and one-sided block implants. The diagnostic system further comprises a plurality of sacrificial circuits adjacent to the IC chip. Moreover, a mis-designed IC chip comprises abnormally functioning circuitry and wherein the known electrical signature of the sacrificial circuit is unique compared to an electrical signature of a normally functioning IC chip. [0013] Another aspect of the invention provides a method for testing an IC during fabrication of the IC, wherein the method comprises fabricating at least one IC chip on a semiconductor wafer; forming a principal circuit adjacent to the IC chip; the principal circuit comprising an electrical signature; forming a sacrificial circuit adjacent to the IC chip, the sacrificial circuit comprising a known electrical signature; comparing the electrical signature of the IC chip with the known electrical signature of the sacrificial circuit, wherein a match in the electrical signature of the IC chip with the known electrical signature of the sacrificial circuit indicates that the IC chip is mis-designed. The method further comprises fabricating a plurality of IC chips on the semiconductor wafer; and configuring a kerf area on the semiconductor wafer for separating one IC chip from another IC chip. Additionally, the method includes forming the sacrificial circuit in the kerf area. In an alternative embodiment, the method includes forming the sacrificial circuit on each of the plurality of IC chips. [0014] The method further comprises intentionally mis-designing the sacrificial circuit with mis-designed circuitry, wherein in the mis-designing process, the mis-designed circuitry comprises any of missing interconnect levels, extraneous interconnect levels, missing source/drain implants, off-specification source/drain implants, missing well implants, off-specification well implants, deposition errors, etching errors, off-specification polysilicon gate thicknesses, missing silicide, ill-formed silicide, missing contacts, ill-formed contacts, field oxide variations, and one-sided block implants. Additionally, the method further comprises forming a plurality of sacrificial circuits on the IC chip. According to the embodiments of the invention, a mis-designed IC chip comprises abnormally functioning circuitry. Also, the known electrical signature of the sacrificial circuit is unique compared to an electrical signature of a normally functioning IC chip. [0015] By purposely mis-designing circuits and components (sacrificial circuits (canary devices)) in known ways, one can create electrical signatures that can be matched against normally-designed failing devices on the same wafers during inline test. Thus, when an electrical signature of a principal device (i.e., device to be tested) matches an electrical signature of a sacrificial device, one can conclude that there is a very high probability that the unintentional processing error in the principal device is the same as the intentional mis-designed error in the sacrificial device having the matching electrical signature, thereby saving costly and time-consuming experiments and low-probability failure analysis. [0016] These and other aspects of the embodiments of the invention will be better appreciated and understood when considered in conjunction with the following description and the accompanying drawings. It should be understood, however, that the following descriptions, while indicating preferred embodiments of the invention and numerous specific details thereof, are given by way of illustration and not of limitation. Many changes and modifications may be made within the scope of the embodiments of the invention without departing from the spirit thereof, and the embodiments of the invention include all such modifications. BRIEF DESCRIPTION OF THE DRAWINGS [0017] The embodiments of the invention will be better understood from the following detailed description with reference to the drawings, in which: [0018] FIG. 1 is a schematic diagram of a diagnostic system according to a first embodiment of the invention; [0019] FIGS. 2(A) and 2(B) are schematic diagrams of a diagnostic system according to a second embodiment of the invention; [0020] FIG. 3 is a schematic diagram of a diagnostic system according to a third embodiment of the invention; [0021] FIG. 4 is a schematic diagram of an implementation of the diagnostic systems of FIGS. 1 through 3 at a wafer level according to an embodiment of the invention; Continue reading... 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