| Calibration circuitry -> Monitor Keywords |
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  Calibration circuitryThe Patent Description & Claims data below is from USPTO Patent Application 20070132619. Brief Patent Description - Full Patent Description - Patent Application Claims
TECHNICAL FIELD [0001] This patent application relates generally to circuitry for calibrating the output of a digital-to-analog converter (DAC). BACKGROUND [0002] Automatic test equipment (ATE) refers to an automated, usually computer-driven, system for testing devices, such as semiconductors, electronic circuits, and printed circuit board assemblies. A device tested by ATE is referred to as a device under test (DUT). [0003] ATE is capable of providing different types of signals to a DUT. Among these signals are test signals, which are used to test the DUT. The test signals may be analog signals that are generated based on digital signals received from a computer or other processing device. A digital-to-analog converter (DAC) (or several DACs) in the ATE is typically used to perform conversion(s) from digital to analog. [0004] A DAC produces an analog signal by sampling a digital signal. A DAC may sample the digital signal using one edge of a clock--the rising or falling edge--or both edges of the clock. Sampling using both edges means that the digital signal is sampled at both the rising and falling edges of the clock. This type of sampling produces a higher sampling rate, and thus a more accurate analog signal. Sampling using both edges of the clock, however, can be quite sensitive to duty cycle errors in the clock. [0005] The duty cycle of a clock is a ratio of the amount of time that the clock is high to the time of one clock cycle. In some systems, an error in the duty cycle occurs if the ratio is anything other than 50%, meaning that the clock is high half of the time and low half of the time. For DACs that sample using both edges of the clock, an error in the duty cycle can result in frequency spurs in output analog signals. SUMMARY [0006] This patent application describes methods and apparatus, including computer program products, for calibrating the output of a circuit, such as a DAC in ATE. [0007] In general, in one aspect, the invention is directed to circuitry that includes a multiplexer to output first data and second data in response to a clock signal, where the clock signal has rising and falling clock edges, and the multiplexer outputs first data at a rising clock edge and outputs second data at a falling clock edge. A digital-to-analog converter (DAC) receives the first data and the second data and generates, therefrom, complementary first and second signals. A filter filters the complementary first signals and second signals and thereby produces first and second filtered signals. A voltmeter measures a difference between the first and second filtered signals. The voltage difference is used in a procedure to obtain and correct for a duty cycle error in the clock signal. This aspect of the invention may also include one or more of the following features. [0008] The filter may be a lowpass filter. The first data and the second data each may include n-bit values, where n>1, that correspond to analog voltage levels. Clock generating circuitry may be used to generate the clock signal. A controller may be used to adjust the clock generating circuitry to substantially compensate for the duty cycle error. The controller may adjust the clock generating circuitry to change the duty cycle of the clock signal. The controller may adjust the clock generating circuitry plural times in order to reduce the duty cycle error. Adjusting the clock generating circuitry plural times may substantially compensate for errors in the duty cycle introduced by the DAC. A tracking circuit may be used to identify a second duty cycle error in the clock signal that was introduced as a result of a change in an operating condition associated with the circuitry, and to substantially compensate for the second duty cycle error. The tracking circuit may include one or more of the following: a multiplexer to output third data and fourth data in response to the clock signal, where the multiplexer outputs third data at a rising clock edge and outputs fourth data at a falling clock edge; a DAC to receive the third data and the fourth data and to output complementary third signals and fourth signals; a lowpass filter to filter the complementary third signals and fourth signals and thereby produce third and fourth filtered signals; and a voltmeter to measure a difference between the third and fourth filtered signals, where the difference corresponds to the second duty cycle error. The third data may include single-bit values having a first voltage level, and the fourth data may include single-bit values having a second voltage level, where the first and second voltage levels are different. The operating condition may include at least one of temperature and voltage applied to power the circuitry. [0009] In general, in another aspect, the invention is directed to a method of calibrating a DAC, which includes outputting first data and second data to the DAC in response to a clock signal having rising and falling clock edges, where the first data is output at a rising clock edge and the second data is output at a falling clock edge. The method also includes generating complementary first signals and second signals via the DAC, where the complementary first signals and second signals are generated based on the first and second data, respectively, filtering the complementary first signals and second signals to produce first and second filtered signals, obtaining a difference between the first and second filtered signals, and adjusting a duty cycle of the clock signal based on the difference. This aspect of the invention may also include one or more of the following. [0010] Filtering may be performed by lowpass filtering. The first data and the second data each may include n-bit values, where n>1, that correspond to analog voltage levels. The duty cycle may be adjusted in order to reduce an error in the duty cycle. The duty cycle may be adjusted plural times in order to substantially compensate for the error in the duty cycle. Adjusting the duty cycle plural times may substantially compensate for errors in the duty cycle introduced by the DAC. The method may also include identifying a second duty cycle error in the clock signal that was introduced as a result of a change in an operating condition associated with the method, and substantially compensating for the second duty cycle error. Identifying the second duty cycle error may include outputting third data and fourth data in response to the clock signal, where the multiplexer outputs third data at a rising clock edge and outputs fourth data at a falling clock edge; generating complementary third signals and fourth signals based on the third data and the fourth data, respectively; filtering the complementary third signals and fourth signals to thereby produce third and fourth filtered signals; and measuring a difference between the third and fourth filtered signals, where the difference corresponds to the second duty cycle error. The third data may include single-bit values having a first voltage level, and the fourth data may include single-bit values having a second voltage level, where the first and second voltage levels are different. The operating condition may include at least one of temperature and voltage applied to power the method. [0011] The details of one or more examples are set forth in the accompanying drawings and the description below. Further features, aspects, and advantages of the invention will become apparent from the description, the drawings, and the claims. DESCRIPTION OF THE DRAWINGS [0012] FIG. 1 is a block diagram of ATE for testing devices. [0013] FIG. 2 is a block diagram of a tester used in the ATE. [0014] FIG. 3 is a diagram of DAC calibration circuitry for use with the ATE. [0015] FIG. 4 is a flowchart showing a process that may be performed using the DAC calibration circuitry. [0016] Like reference numerals in different figures indicate like elements. DETAILED DESCRIPTION [0017] Referring to FIG. 1, a system 10 for testing a device-under-test (DUT) 18, such as a semiconductor device, includes a tester 12 such as automatic test equipment (ATE) or other similar testing device. To control tester 12, system 10 includes a computer system 14 that interfaces with tester 12 over a hardwire connection 16. Typically, computer system 14 sends commands to tester 12 that initiate the execution of routines and functions for testing DUT 18. Such executing test routines may initiate the generation and transmission of test signals to the DUT 18 and collection of responses from the DUT. Various types of DUTs may be tested by system 10. For example, DUTs may be semiconductor devices, such as an integrated circuit (IC) chip (e.g., memory chip, microprocessor, analog-to-digital converter, digital-to-analog converter, etc.). [0018] To provide test signals and collect responses from the DUT, tester 12 is connected to one or more connector pins that provide an interface for the internal circuitry of DUT 18. To test some DUTs, e.g., as many as sixty-four or one hundred twenty-eight connector pins (or more) may be interfaced to tester 12. For illustrative purposes, in this example, semiconductor device tester 12 is connected to one connector pin of DUT 18 via a hardwire connection. A conductor 20 (e.g., cable) is connected to pin 22 and is used to deliver test signals (e.g., PMU test signals, PE test signals, etc.) to the internal circuitry of DUT 18. Conductor 20 also senses signals at pin 22 in response to the test signals provided by semiconductor device tester 12. For example, a voltage signal or a current signal may be sensed at pin 22 in response to a test signal and sent over conductor 20 to tester 12 for analysis. Such single port tests may also be performed on other pins included in DUT 18. For example, tester 12 may provide test signals into other pins and collect associated signals reflected back over conductors (that deliver the provided signals). By collecting the reflected signals, the input impedance of the pins may be characterized, along with other single port testing quantities. In other test scenarios, a digital signal may be sent over conductor 20 to pin 22 for storing a digital value on DUT 18. Once stored, DUT 18 may be accessed to retrieve and send the stored digital value over conductor 20 to tester 12. The retrieved digital value may then be identified to determine if the proper value was stored on DUT 18. [0019] Along with performing one-port measurements, a two-port test may also be performed by semiconductor device tester 12. For example, a test signal may be injected over conductor 20 into pin 22 and a response signal may be collected from one or more other pins of DUT 18. This response signal may be provided to semiconductor device tester 12 to determine such quantities as gain response, phase response, and other throughput measurement quantities. Continue reading... Full patent description for Calibration circuitry Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Calibration circuitry patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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