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01/17/08 - USPTO Class 414 | 9 views | #20080014055 | Prev - Next | About this Page

Bypass thermal adjuster for vacuum semiconductor processing

Title: Bypass thermal adjuster for vacuum semiconductor processing

Related Patent Categories: Material Or Article Handling, Chamber Of A Type Utilized For A Heating Function And Material Charging Or Discharging Means Therefor, Charging Of Chamber, By Driven Device For Transporting Material To And/or Into, Or Into And Within, Chamber, Plural, Successive, Driven Devices

Brief Patent Description - Full Patent Description - Patent Claims

The Patent Description & Claims data below is from USPTO Patent Application 20080014055, Bypass thermal adjuster for vacuum semiconductor processing.

1. A system comprising: a vacuum module in a semiconductor manufacturing system; a sealable enclosure within an interior of the vacuum module, the sealable enclosure including a support for at least one wafer, and the sealable enclosure capable of selectively isolating an environment within the sealable enclosure from the interior of the vacuum module; and a thermal management system that controls a temperature of the at least one wafer within the sealable enclosure.

2. The system of claim 1 further comprising a plurality of sealable enclosures within the interior of the vacuum module.

3. The system of claim 1 further comprising a plurality of entries to the vacuum module for access by a robotic wafer handler.

4. The system of claim 1 further comprising a vacuum management system to control a vacuum within the environment of the sealable enclosure.

5. (canceled)

6. The system of claim 1 wherein the environment of the sealable enclosure is selected from a group consisting of a nitrogen environment, an argon environment, and a helium environment.

7. The system of claim 1 wherein the thermal management system cools the at least one wafer.

8. The system of claim 1 wherein the thermal management system heats the at least one wafer.

9. The system of claim 1 wherein the thermal management system directly contacts the wafer.

10. The system of claim 1 wherein the vacuum module is coupled to a semiconductor fabrication system.

11. The system of claim 1 wherein the vacuum module permits additional wafers to pass through the interior while the sealable enclosure holds the at least one wafer in isolation.

12. The system of claim 1 further comprising a second sealable enclosure within the interior of the vacuum module, the second sealable enclosure including a second support for at least one second wafer, and the second sealable enclosure capable of selectively isolating a second environment within the second sealable enclosure from the interior of the vacuum module.

13. The system of claim 12 wherein the second sealable enclosure is vertically stacked with the sealable enclosure.

14. The system of claim 12 wherein the second sealable enclosure can be isolated independently from the sealable enclosure.

15. The system of claim 12 wherein the sealable enclosure and the second sealable enclosure operate in opposition, whereby only one of the enclosures may be isolated at one time.

16. The system of claim 12 wherein the vacuum module permits additional wafers to pass through the interior while the sealable enclosure holds the at least one wafer in isolation.

17. The system of claim 16 wherein the vacuum module permits additional wafers to pass through the interior while the second sealable enclosure holds the at least one second wafer in isolation.

18. The system of claim 1 wherein the sealable enclosure includes one or more slot valves.

19. A method comprising: receiving a first wafer in a vacuum module; isolating the first wafer in an isolation environment; heating the first wafer in the isolation environment; and passing a second wafer through the vacuum module while heating the first wafer.

20. The method of claim 19 wherein passing the second wafer through the vacuum module includes temporarily storing the second wafer in the vacuum module and passing a third wafer through the vacuum module while temporarily storing the second wafer.

21. (canceled)

22. A system comprising: a vacuum module in a semiconductor manufacturing system; an enclosure within an interior of the vacuum module, the enclosure including a support for at least one wafer, and the enclosure capable moving a wafer out of a path through the vacuum module; and a thermal management system adapted to control a temperature of the wafer while at least one other wafer is passed through the interior.

Brief Patent Description - Full Patent Description - Patent Claims

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