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Brent A. ANDERSON patents

Recent bibliographic sampling of Brent A. ANDERSON patents listed/published in the public domain by the USPTO (USPTO Patent Application #,Title):



05/21/15 - 20150137267 - Replacement gate structures and methods of manufacturing
Gate structures and methods of manufacturing is disclosed. The method includes forming a continuous replacement gate structure within a trench formed in dielectric material. The method further includes segmenting the continuous replacement gate structure into separate replacement gate structures. The method further includes forming insulator material between the separate replacement...
Inventors: Brent A. Anderson, Edward J. Nowak (International Business Machines Corporation)

02/12/15 - 20150041904 - Blanket short channel roll-up implant with non-angled long channel compensating implant through patterned opening
A method that forms a structure implants a well implant into a substrate, patterns a mask on the substrate (to have at least one opening that exposes a channel region of the substrate) and forms a conformal dielectric layer on the mask and to line the opening. The conformal dielectric...
Inventors: James W. Adkisson, Brent A. Anderson, Andres Bryant, Edward J. Nowak (International Business Machines Corporation)

02/05/15 - 20150040084 - Structure, method and system for complementary strain fill for integrated circuit chips
A structure, method and system for complementary strain fill for integrated circuit chips. The structure includes a first region of an integrated circuit having multiplicity of n-channel and p-channel field effect transistors (FETs); a first stressed layer over n-channel field effect transistors (NFETs) of the first region, the first stressed...
Inventors: Brent A. Anderson, Edward J. Nowak, Jed H. Rankin (International Business Machines Corporation)

02/05/15 - 20150035059 - Method, structure and design structure for customizing history effects of soi circuits
A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a high-leakage dielectric formed over an active region of a FET and a low-leakage dielectric formed on the active region and adjacent the high-leakage dielectric. The low-leakage dielectric has...
Inventors: Brent A. Anderson, Andres Bryant, Edward J. Nowak (International Business Machines Corporation)

02/05/15 - 20150035026 - Middle-of-line borderless contact structure and method of forming
Various embodiments disclosed include semiconductor structures and methods of forming such structures. In one embodiment, a method includes: providing a semiconductor structure including: a substrate; at least one gate structure overlying the substrate; and an interlayer dielectric overlying the substrate and the at least one gate structure; removing the ILD...
Inventors: Brent A. Anderson, David V. Horak, Edward J. Nowak (International Business Machines Corporation)

01/15/15 - 20150014774 - Merged tapered finfet
According to a structure herein, parallel fins comprise channel regions and source and drain regions. Parallel gate conductors are over and intersecting the channel regions of the fins. Electrical insulator material surrounds sides of the gate conductors. Each of the fins has a main fin body and wider regions extending...
Inventors: Brent A. Anderson, Edward J. Nowak (International Business Machines Corporation)

11/13/14 - 20140332888 - Semiconductor device including finfet structures with varied epitaxial regions, related method and design structure
A semiconductor device including a substrate; a FINFET disposed on the substrate, the FINFET including: a set of epitaxial regions disposed in a source/drain region on a set of fins, the set of epitaxial regions including: a first epitaxial region on a first inner surface of a first outer fin,...
Inventors: Brent A. Anderson, Edward J. Nowak (International Business Machines Corporation)

05/01/14 - 20140117450 - Partially depleted (pd) semiconductor-on-insulator (soi) field effect transistor (fet) structure with a gate-to-body tunnel current region for threshold voltage (vt) lowering and method of forming the structure
Disclosed are embodiments of a field effect transistor with a gate-to-body tunnel current region (GTBTCR) and a method. In one embodiment, a gate, having adjacent sections with different conductivity types, traverses the center portion of a semiconductor layer to create, within the center portion, a channel region and a GTBTCR...
Inventors: Brent A. Anderson, Andres Bryant, Jiale Liang, Edward J. Nowak (International Business Machines Corporation)

04/24/14 - 20140110767 - Bulk finfet well contacts with fin pattern uniformity
Bulk finFET well contacts with fin pattern uniformity and methods of manufacture. The method includes providing a substrate with a first region and a second region, the first region comprising a well with a first conductivity. The method further includes forming contiguous fins over the first region and the second...
Inventors: Brent A. Anderson, Andres Bryant, Edward J. Nowak, Scott R. Stiffler (International Business Machines Corporation)

03/20/14 - 20140077276 - Middle-of-line borderless contact structure and method of forming
Various embodiments disclosed include semiconductor structures and methods of forming such structures. In one embodiment, a method includes: providing a semiconductor structure including: a substrate; at least one gate structure overlying the substrate; and an interlayer dielectric overlying the substrate and the at least one gate structure; removing the ILD...
Inventors: Brent A. Anderson, David V. Horak, Edward J. Nowak (International Business Machines Corporation)

03/13/14 - 20140070330 - Method of forming a field effect transistor having a gate structure with a first section having a first effective work function above a center portion of the channel region and with second sections having a second effective work function above opposing sidewalls of the channel region
In view of the foregoing, disclosed herein are embodiments of an improved field effect transistor (FET) structure and a method of forming the structure. The FET structure embodiments each incorporate a unique gate structure. Specifically, this gate structure has a first section above a center portion of the FET channel...
Inventors: Brent A. Anderson, Edward J. Nowak (International Business Machines Corporation)

03/06/14 - 20140061139 - Nano-filter and method of forming same, and method of filtration
The disclosure relates generally to nano-filters and methods of forming same, and methods of filtration. The nano-filter includes a substrate and at least one nanowire structure located between an inlet and an outlet. The nanowire structure may include a plurality of vertically stacked horizontal nanowires....
Inventors: Brent A. Anderson, Andres Bryant, Edward J. Nowak, Jeffrey W. Sleight (International Business Machines Corporation)

01/23/14 - 20140021554 - Source/drain-to-source/drain recessed strap and methods of manufacture of same
A structure and a method of making the structure. The structure includes first and second semiconductor regions in a semiconductor substrate and separated by a region of trench isolation in the semiconductor substrate; a first gate electrode extending over the first semiconductor region; a second gate electrode extending over the...
Inventors: Brent A. Anderson, Edward J. Nowak, Jed H. Rankin (International Business Machines Corporation)

11/14/13 - 20130299908 - Simultaneous formation of finfet and mugfet
A method and structure comprise a field effect transistor structure that includes a first rectangular fin structure positioned on a substrate. The first rectangular fin structure has a bottom contacting the substrate, a top opposite the bottom, and sides between the top and the bottom. The structure additionally includes a...
Inventors: Brent A. Anderson, Edward J. Nowak, Jed H. Rankin

10/31/13 - 20130285145 - Formation of multi-height mugfet
A method and structure comprise a field effect transistor structure that includes a first rectangular fin structure and a second rectangular fin structure, both positioned on a substrate. The sides of the second rectangular fin structure are parallel to the sides of the first rectangular fin structure. Further, a trench...
Inventors: Brent A. Anderson, Edward J. Nowak, Jed H. Rankin

10/17/13 - 20130270644 - Replacement gate structures and methods of manufacturing
Gate structures and methods of manufacturing is disclosed. The method includes forming a continuous replacement gate structure within a trench formed in dielectric material. The method further includes segmenting the continuous replacement gate structure into separate replacement gate structures. The method further includes forming insulator material between the separate replacement...
Inventors: Brent A. Anderson, Edward J. Nowak (International Business Machines Corporation)

09/19/13 - 20130240997 - Contact bars for modifying stress in semiconductor device and related method
Solutions for forming stress optimizing contact bars and contacts are disclosed. In one aspect, a semiconductor device is disclosed including an n-type field effect transistor (NFET) having source/drain regions; a p-type field effect transistor (PFET) having source/drain regions; a stress inducing layer over both the NFET and the PFET, the...
Inventors: Brent A. Anderson, Andres Bryant, William F. Clark, Jr., Edward J. Nowak (International Business Machines Corporation)

09/05/13 - 20130230960 - Structure fabrication method
A structure fabrication method. A provided structure includes a gate dielectric region on the substrate and a gate electrode region on the gate dielectric region. Atoms are implanted in a top portion of the gate electrode region, which expands the top portion of the gate electrode in a direction parallel...
Inventors: Brent A. Anderson, Victor W. C. Chan, Edward J. Nowak (International Business Machines Corporation)

08/22/13 - 20130217198 - Localized implant into active region for enhanced stress
Methods for enhancing strain in an integrated circuit are provided. Embodiments of the invention include using a localized implant into an active region prior to a gate etch. In another embodiment, source/drain regions adjacent to the gates are recessed to allow the strain to expand to full potential. New source/drain...
Inventors: Brent A. Anderson, Edward J. Nowak (International Business Machines Corporation)

08/08/13 - 20130200458 - Devices with gate-to-gate isolation structures and methods of manufacture
Devices having gate-to-gate isolation structures and methods of manufacture are provided. The method includes forming a plurality of isolation structures in pad films and an underlying substrate. The method further includes forming a plurality of fins including the isolation structures and a second plurality of fins including the two pad...
Inventors: Brent A. Anderson, Edward J. Nowak, Jed H. Rankin (International Business Machines Corporation)

08/08/13 - 20130200454 - Replacement-gate finfet structure and process
A fin field effect transistor (FinFET) structure and method of making the FinFET including a silicon fin that includes a channel region and source/drain (S/D) regions, formed on each end of the channel region, where an entire bottom surface of the channel region contacts a top surface of a lower...
Inventors: Brent A. Anderson, Andres Bryant, Edward J. Nowak (International Business Machines Corporation)

07/25/13 - 20130187243 - Method, structure and design structure for customizing history effects of soi circuits
A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a high-leakage dielectric formed over an active region of a FET and a low-leakage dielectric formed on the active region and adjacent the high-leakage dielectric. The low-leakage dielectric has...
Inventors: Brent A. Anderson, Andres Bryant, Edward J. Nowak (International Business Machines Corporation)

07/11/13 - 20130175651 - Damascene metal gate and shield structure, methods of manufacture and design structures
Semiconductor structures with damascene metal gates and pixel sensor cell shields, methods of manufacture and design structures are provided. The method includes forming a dielectric layer over a dummy gate structure. The method further includes forming one or more recesses in the dielectric layer. The method further includes removing the...
Inventors: Brent A. Anderson, Andres Bryant, William F. Clark, Jr., John J. Ellis-monaghan, Edward J. Nowak (International Business Machines Corporation)

07/04/13 - 20130171796 - Methods of fabricating trench generated device structures
Methods for fabricating device structures, such as bipolar transistors and diodes. The method includes forming a trench extending through stacked semiconductor and insulator layers and into an underlying semiconductor substrate. The trench may be at least partially filled with a sacrificial plug containing a dopant with a conductivity type opposite...
Inventors: Brent A. Anderson, Edward J. Nowak (International Business Machines Corporation)

07/04/13 - 20130171780 - Body contacted hybrid surface semiconductor-on-insulator devices
A portion of a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate is patterned into a semiconductor fin having substantially vertical sidewalls. A portion of a body region of the semiconductor fin is exposed on a top surface of the semiconductor fin between two source regions having a doping of...
Inventors: Brent A. Anderson, Edward J. Nowak (International Business Machines Corporation)

06/27/13 - 20130164910 - Devices with gate-to-gate isolation structures and methods of manufacture
Devices having gate-to-gate isolation structures and methods of manufacture are provided. The method includes forming a plurality of isolation structures in pad films and an underlying substrate. The method further includes forming a plurality of fins including the isolation structures and a second plurality of fins including the two pad...
Inventors: Brent A. Anderson, Edward J. Nowak, Jed H. Rankin (International Business Machines Corporation)

06/27/13 - 20130164877 - Isolation structures for global shutter imager pixel, methods of manufacture and design structures
Pixel sensor cells, e.g., CMOS optical imagers, methods of manufacturing and design structures are provided with isolation structures that prevent carrier drift to diffusion regions. The pixel sensor cell includes a photosensitive region and a gate adjacent to the photosensitive region. The pixel sensor cell further includes a diffusion region...
Inventors: Brent A. Anderson, Mark D. Jaffe (International Business Machines Corporation)

06/27/13 - 20130161748 - Structure, method and system for complementary strain fill for integrated circuit chips
A structure, method and system for complementary strain fill for integrated circuit chips. The structure includes a first region of an integrated circuit having multiplicity of n-channel and p-channel field effect transistors (FETs); a first stressed layer over n-channel field effect transistors (NFETs) of the first region, the first stressed...
Inventors: Brent A. Anderson, Edward J. Nowak, Jed H. Rankin (International Business Machines Corporation)

06/27/13 - 20130161747 - Isolation region fabrication for replacement gate processing
A semiconductor structure includes a silicon-on-insulator (SOI) substrate, the SOI substrate comprising a bottom silicon layer, a buried oxide (BOX) layer, and a top silicon layer; a plurality of active devices formed on the top silicon layer; and an isolation region located between two of the active devices, wherein at...
Inventors: Brent A. Anderson, Edward J. Nowak (International Business Machines Corporation)

06/20/13 - 20130154003 - Asymmetric anti-halo field effect transistor
A method of forming an integrated circuit structure implants a first compensating implant into a substrate. The method patterns a mask on the first compensating implant in the substrate. The mask includes an opening exposing a channel location of the substrate. The method implants a second compensating implant into the...
Inventors: James W. Adkisson, Brent A. Anderson, Andres Bryant, Edward J. Nowak (International Business Machines Corporation)

06/13/13 - 20130146139 - Low cost solar cell manufacture method employing a reusable substrate
A reusable substrate and method for forming single crystal silicon solar cells are described. A method of forming a photovoltaic cell includes forming an intermediate layer on a monocrystalline silicon substrate, forming a monocrystalline silicon layer on the intermediate layer, and forming electrical features in the monocrystalline silicon layer. The...
Inventors: Brent A. Anderson, Edward J. Nowak, Jed H. Rankin (International Business Machines Corporation)

05/23/13 - 20130132924 - Method, structure and design structure for customizing history effects of soi circuits
A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a structure which comprises a high-leakage dielectric formed in a divot on each side of a segmented FET comprised of active silicon islands and gate electrodes thereon, and a...
Inventors: Brent A. Anderson, Edward J. Nowak (International Business Machines Corporation)

05/16/13 - 20130122668 - Method for forming and structure of a recessed source/drain strap for a mugfet
A method and semiconductor structure includes an insulator layer on a substrate, a plurality of parallel fins above the insulator layer. Each of the fins has a central semiconductor portion and conductive end portions. At least one conductive strap is positioned within the insulator layer below the fins. The conductive...
Inventors: Brent A. Anderson, Andres Bryant, Edward J. Nowak, Jed H. Rankin (International Business Machines Corporation)

05/16/13 - 20130119447 - Non-uniform gate dielectric charge for pixel sensor cells and methods of manufacturing
A non-uniform gate dielectric charge for pixel sensor cells, e.g., CMOS optical imagers, and methods of manufacturing are provided. The method includes forming a gate dielectric on a substrate. The substrate includes a source/drain region and a photo cell collector region. The method further includes forming a non-uniform fixed charge...
Inventors: Brent A. Anderson, Andres Bryant, William F. Clark, Jr., John J. Ellis-monaghan, Edward J. Nowak (International Business Machines Corporation)

05/09/13 - 20130113050 - Blanket short channel roll-up implant with non-angled long channel compensating implant through patterned opening
A method that forms a structure implants a well implant into a substrate, patterns a mask on the substrate (to have at least one opening that exposes a channel region of the substrate) and forms a conformal dielectric layer on the mask and to line the opening. The conformal dielectric...
Inventors: James W. Adkisson, Brent A. Anderson, Andres Bryant, Edward J. Nowak (International Business Machines Corporation)

04/11/13 - 20130089815 - Chromeless phase-shifting photomask with undercut rim-shifting element
A phase-shifting photomask with a self aligned undercut rim-shifting element and methods for its manufacture are provided. One embodiment of the invention provides a method of manufacturing a phase-shifting photomask having a self aligned rim-shifting element, the method comprising: applying a patterning film to a first portion of a transparent...
Inventors: Brent A. Anderson, Jed H. Rankin (International Business Machines Corporation)

03/14/13 - 20130065370 - Method for fabricating field effect transistor devices with high-aspect ratio mask
A method for forming feature on a substrate includes forming at least one layer of a feature material on a substrate, patterning a photolithographic resist material on the at least one layer of the feature material, removing portions of the feature material to define a feature, depositing a masking material...
Inventors: Brent A. Anderson, Edward J. Nowak, Jed H. Rankin (International Business Machines Corporation)

03/14/13 - 20130062687 - Sram cell having recessed storage node connections and method of fabricating same
An SRAM cell and a method of forming an SRAM cell. The SRAM cell includes a first pass gate field effect transistor (FET) and a first pull-down FET sharing a first common source/drain (S/D) and a first pull-up FET having first and second S/Ds; a second pass gate FET and...
Inventors: Brent A. Anderson, Edward J. Nowak, Jed H. Rankin (International Business Machines Corporation)

03/07/13 - 20130056805 - Transistors having stressed channel regions and methods of forming transistors having stressed channel regions
A method of forming a field effect transistor and a field effect transistor. The method includes (a) forming gate stack on a silicon layer of a substrate; (b) forming two or more SiGe filled trenches in the silicon layer on at least one side of the gate stack, adjacent pairs...
Inventors: Brent A. Anderson, Edward J. Nowak (International Business Machines Corporation)

02/21/13 - 20130043535 - Isolation region fabrication for replacement gate processing
A method for isolation region fabrication for replacement gate integrated circuit (IC) processing includes forming a plurality of dummy gates on a substrate; forming a block mask over the plurality of dummy gates, such that the block mask selectively exposes a dummy gate of the plurality of dummy gates; removing...


02/21/13 - 20130043412 - Serial irradiation of a substrate by multiple radiation sources
A system for configuring and utilizing J electromagnetic radiation sources (J≧2) to serially irradiate a substrate. Each source has a different function of wavelength and angular distribution of emitted radiation. The substrate includes a base layer and I stacks (I≧2; J≦I) thereon. Pj denotes a normally incident energy flux on...


01/17/13 - 20130015515 - Fet edram trench self-aligned to buried strap
A structure and method of making a field effect transistor (FET) embedded dynamic random access memory (eDRAM) cell array, which includes: a buried silicon strap extending into a buried oxide (BOX) layer of a silicon-on-insulator (SOI) substrate; a recessed trench capacitor extending down into the substrate layer of the SOI...


12/06/12 - 20120306016 - Devices with gate-to-gate isolation structures and methods of manufacture
A method includes forming a plurality of trenches in a pad film to form raised portions, and depositing a hard mask in the trenches and over the upper pad film. The method includes forming a plurality of fins including the raised portions and a second plurality of fins including the...


11/29/12 - 20120301990 - Pixel sensor cell with a dual work function gate electode
Pixel sensor cells, methods of fabricating pixel sensor cells, and design structures for a pixel sensor cell. The pixel sensor cell has a gate structure that includes a gate dielectric and a gate electrode on the gate dielectric. The gate electrode includes a layer with first and second sections that...


11/22/12 - 20120292704 - Barrier trench structure and methods of manufacture
A method includes forming at least one shallow trench isolation structure in a substrate to isolate adjacent different type devices. The method further includes forming a barrier trench structure in the substrate to isolate diffusions of adjacent same type devices. The method further includes spanning the barrier trench structure with...


11/01/12 - 20120273895 - Damascene method of forming a semiconductor structure and a semiconductor structure with multiple fin-shaped channel regions having different widths
Disclosed is a damascene method for forming a semiconductor structure and the resulting semiconductor structure having multiple fin-shaped channel regions with different widths. In the method, fin-shaped channel regions are etched using differently configured isolating caps as masks to define the different widths. For example, a wide width isolating cap...


10/25/12 - 20120267726 - Dual metal gate corner
In view of the foregoing, disclosed herein are embodiments of an improved field effect transistor (FET) structure and a method of forming the structure. The FET structure embodiments each incorporate a unique gate structure. Specifically, this gate structure has a first section above a center portion of the FET channel...


09/27/12 - 20120241857 - Dual stress device and method
A semiconductor device including semiconductor material having a bend and a trench feature formed at the bend, and a gate structure at least partially disposed in the trench feature. A method of fabricating a semiconductor structure including forming a semiconductor material with a trench feature over a layer, forming a...


09/20/12 - 20120235216 - Damascene metal gate and shield structure, methods of manufacture and design structures
Semiconductor structures with damascene metal gates and pixel sensor cell shields, methods of manufacture and design structures are provided. The method includes forming a dielectric layer over a dummy gate structure. The method further includes forming one or more recesses in the dielectric layer. The method further includes removing the...


09/13/12 - 20120228709 - Integrated circuit structure incorporating one or more asymmetric field effect transistors as power gates for an electronic circuit with stacked symmetric field effect transistors
Disclosed is an integrated circuit having an asymmetric FET as a power gate for an electronic circuit, which has at least two stacked symmetric field effect transistors. The asymmetric FET has an asymmetric halo configuration (i.e., a single source-side halo or a source-side halo with a higher dopant concentration than...


08/23/12 - 20120211854 - Pixel sensor cell with a dual work function gate electode
Pixel sensor cells, methods of fabricating pixel sensor cells, and design structures for a pixel sensor cell. The pixel sensor cell has a gate structure that includes a gate dielectric and a gate electrode on the gate dielectric. The gate electrode includes a layer with first and second sections that...


08/16/12 - 20120208328 - Body contacted hybrid surface semiconductor-on-insulator devices
A portion of a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate is patterned into a semiconductor fin having substantially vertical sidewalls. A portion of a body region of the semiconductor fin is exposed on a top surface of the semiconductor fin between two source regions having a doping of...


07/26/12 - 20120190156 - Recessed gate channel with low vt corner
A recessed gate FET device includes a substrate having an upper and lower portions, the lower portion having a reduced concentration of dopant material than the upper portion; a trench-type gate electrode defining a surrounding channel region and having a gate dielectric material layer lining and including a conductive material...


07/26/12 - 20120188008 - Circuit with stacked structure and use thereof
A circuit has a stacked structure having at least one symmetric FET at a bottom of the stack. More particularly, the circuit has a stacked structure which includes an asymmetric FET and a symmetric FET. The symmetric FET is placed at the bottom of the stacked structure closer to ground...


07/19/12 - 20120183889 - Multiple lithographic system mask shape sleeving
A mask fabrication method can include receiving a mask design, sending first exposure parameters to a first exposure machine, sending second exposure parameters to a second exposure machine, sending a first exposure generation command to the first machine based on the first exposure parameters and sending a second exposure generation...


07/19/12 - 20120181588 - Pixel sensor cells with a split-dielectric transfer gate
Pixel sensor cells, methods of fabricating pixel sensor cells, and design structures for a pixel sensor cell. A transistor in the pixel sensor cell has a gate structure that includes a gate dielectric with a thick region and a thin region. A gate electrode of the gate structure is formed...


07/05/12 - 20120168873 - Transmission gates with asymmetric field effect transistors
Transmission gates, methods of fabricating transmission gates, and design structures for a transmission gate. The transmission gate includes an n-channel field effect transistor characterized by terminals that are asymmetrically doped and a p-channel field effect transistor characterized by terminals that are asymmetrically doped....


07/05/12 - 20120168866 - Structure, method and system for complementary strain fill for integrated circuit chips
A structure, method and system for complementary strain fill for integrated circuit chips. The structure includes a first region of an integrated circuit having multiplicity of n-channel and p-channel field effect transistors (FETs); a first stressed layer over n-channel field effect transistors (NFETs) of the first region, the first stressed...


07/05/12 - 20120168832 - Asymmetric field effect transistor structure and method
Disclosed are embodiments of an asymmetric field effect transistor structure and a method of forming the structure in which both series resistance in the source region (Rs) and gate to drain capacitance (Cgd) are reduced in order to provide optimal performance (i.e., to provide improved drive current with minimal circuit...


06/21/12 - 20120156838 - Multi-gate non-planar field effect transistor structure and method of forming the structure using a dopant implant process to tune device drive current
Disclosed are embodiments of a semiconductor structure that includes one or more multi-gate field effect transistors (MUGFETs), each MUGFET having one or more semiconductor fins. In the embodiments, dopant implant region is incorporated into the upper portion of the channel region of a semiconductor fin in order to selectively modify...


06/21/12 - 20120153431 - Integrated circuit and a method using integrated process steps to form deep trench isolation structures and deep trench capacitor structures for the integrated circuit
Disclosed is an integrated circuit having at least one deep trench isolation structure and a deep trench capacitor. A method of forming the integrated circuit incorporates a single etch process to simultaneously form first trench(s) and a second trenches for the deep trench isolation structure(s) and a deep trench capacitor,...


06/21/12 - 20120153353 - Buried oxidation for enhanced mobility
A method patterns at least one pair of openings through a protective layer and into a substrate. The openings are positioned on opposite sides of a channel region of the substrate. The method forms sidewall spacers along the sidewalls of the openings and removes additional substrate material from the bottom...


06/14/12 - 20120146187 - Methods and structures for increased thermal dissipation of thin film resistors
A method of forming a semiconductor structure includes forming at least one trench in an insulator layer formed on a substrate. A distance between a bottom edge of the at least one trench and a top surface of a substrate is shorter than a distance between an uppermost surface of...


06/14/12 - 20120146146 - Partially depeleted (dp) semiconductor-on-insulator (soi) field effect transistor (fet) structure with a gate-to-body tunnel current region for threshold voltage (vt) lowering and method of forming the structure
Disclosed are embodiments of a field effect transistor with a gate-to-body tunnel current region (GTBTCR) and a method. In one embodiment, a gate, having adjacent sections with different conductivity types, traverses the center portion of a semiconductor layer to create, within the center portion, a channel region and a GTBTCR...


06/14/12 - 20120146145 - Semiconductor structure and methods of manufacture
FinFET end-implanted-semiconductor structures and methods of manufacture are disclosed herein. The method includes forming at least one mandrel on a silicon layer of a substrate comprising an underlying insulator layer. The method further includes etching the silicon layer to form at least one silicon island under the at least one...


06/14/12 - 20120145650 - Nano-filter and method of forming same, and method of filtration
The disclosure relates generally to nano-filters and methods of forming same, and methods of filtration. The nano-filter includes a substrate and at least one nanowire structure located between an inlet and an outlet. The nanowire structure may include a plurality of vertically stacked horizontal nanowires....


05/31/12 - 20120133000 - Field effect transistor with channel region edge and center portions having different band structures for suppressed corner leakage
Disclosed are embodiments of field effect transistors (FETs) having suppressed sub-threshold corner leakage, as a function of channel material band-edge modulation. Specifically, the FET channel region is formed with different materials at the edges as compared to the center. Different materials with different band structures and specific locations of those...


05/24/12 - 20120126337 - Source/drain-to-source/drain recessed strap and methods of manufacture of same
A structure and a method of making the structure. The structure includes first and second semiconductor regions in a semiconductor substrate and separated by a region of trench isolation in the semiconductor substrate; a first gate electrode extending over the first semiconductor region; a second gate electrode extending over the...


05/24/12 - 20120126336 - Isolation fet for integrated circuit
An integrated circuit (IC) includes an active region; a pair of active field effect transistors (FETs) in the active region; and an isolation FET located between the pair of active FETs in the active region, the isolation FET configured to provide electrical isolation between the pair of active FETs, wherein...


05/24/12 - 20120125421 - Low cost solar cell manufacture method employing a reusable substrate
A reusable substrate and method for forming single crystal silicon solar cells are described. A method of forming a photovoltaic cell includes forming an intermediate layer on a monocrystalline silicon substrate, forming a monocrystalline silicon layer on the intermediate layer, and forming electrical features in the monocrystalline silicon layer. The...


05/17/12 - 20120119296 - Trench-generated transistor structures, device structures, and design structures
Trench-generated transistor structures, design structures for a trench-generated transistor, and other trench-generated device structures. The source and drain of the transistor are defined by doped regions in the semiconductor material of the handle substrate of a semiconductor-on-insulator (SOI) wafer. The gate electrode may be defined from the semiconductor layer of...


05/17/12 - 20120119284 - Semiconductor structures and methods of manufacture
Semiconductor structures and methods of manufacture semiconductors are provided which relate to transistors. The method of forming a transistor includes thermally annealing a selectively patterned dopant material formed on a high-k dielectric material to form a high charge density dielectric layer from the high-k dielectric material. The high charge density...


05/10/12 - 20120112287 - Gate-to-gate recessed strap and methods of manufacture of same
A structure and methods of making the structure. The structure includes: first and a second semiconductor regions in a semiconductor substrate and separated by a region of trench isolation in the substrate; a first gate electrode extending over the first semiconductor region and the region of the trench isolation; a...


05/10/12 - 20120112284 - Strained semiconductor devices and methods of fabricating strained semiconductor devices
A structure and method of fabricating the structure. The structure includes a first region of a semiconductor substrate separated from a second region of the semiconductor substrate by trench isolation formed in the substrate; a first stressed layer over the first region; a second stressed layer over second region; the...


05/10/12 - 20120112206 - Asymmetric hetero-structure fet and method of manufacture
An asymmetric hetero-structure FET and method of manufacture is provided. The structure includes a semiconductor substrate and an epitaxially grown semiconductor layer on the semiconductor substrate. The epitaxially grown semiconductor layer includes an alloy having a band structure and thickness that confines inversion carriers in a channel region, and a...


05/03/12 - 20120104538 - Damascene method of forming a semiconductor structure and a semiconductor structure with multiple fin-shaped channel regions having different widths
Disclosed is a damascene method for forming a semiconductor structure and the resulting semiconductor structure having multiple fin-shaped channel regions with different widths. In the method, fin-shaped channel regions are etched using differently configured isolating caps as masks to define the different widths. For example, a wide width isolating cap...


04/26/12 - 20120100685 - Localized implant into active region for enhanced stress
Methods for enhancing strain in an integrated circuit are provided. Embodiments of the invention include using a localized implant into an active region prior to a gate etch. In another embodiment, source/drain regions adjacent to the gates are recessed to allow the strain to expand to full potential. New source/drain...


04/26/12 - 20120100674 - Semiconductor structure and methods of manufacture
FinFET end-implanted-semiconductor structures and methods of manufacture are disclosed herein. The method includes forming at least one mandrel on a silicon layer of a substrate comprising an underlying insulator layer. The method further includes etching the silicon layer to form at least one silicon island under the at least one...


04/26/12 - 20120098068 - Formation of multi-height mugfet
A method and structure comprise a field effect transistor structure that includes a first rectangular fin structure and a second rectangular fin structure, both positioned on a substrate. The sides of the second rectangular fin structure are parallel to the sides of the first rectangular fin structure. Further, a trench...


04/26/12 - 20120098066 - Simultaneous formation of finfet and mugfet
A method and structure comprise a field effect transistor structure that includes a first rectangular fin structure position on a substrate. The first rectangular fin structure has a bottom contacting the substrate, a top opposite the bottom, and sides between the top and the bottom. The structure additionally includes a...


04/19/12 - 20120094465 - Integrated planar and multiple gate fets
A multiple gate field effect transistor and a planar field effect transistor formed in the same substrate each have a top planar surface underneath each corresponding gate that are co-planar with one another and also co-planar with a top surface of a shallow trench isolation region located therebetween. The relatively...


04/12/12 - 20120086083 - Devices with gate-to-gate isolation structures and methods of manufacture
Devices having gate-to-gate isolation structures and methods of manufacture are provided. The method includes forming a plurality of isolation structures in a pad film and an underlying substrate. The method further includes protecting at least one of the plurality of isolation structures in order to preserve its height. The method...


04/12/12 - 20120086078 - Devices with gate-to-gate isolation structures and methods of manufacture
Devices having gate-to-gate isolation structures and methods of manufacture are provided. The method includes forming a plurality of isolation structures in pad films and an underlying substrate. The method further includes forming a plurality of fins including the isolation structures and a second plurality of fins including the two pad...


04/12/12 - 20120086055 - Devices with gate-to-gate isolation structures and methods of manufacture
Devices having gate-to-gate isolation structures and methods of manufacture are provided. The method includes forming a plurality of trenches in a pad film to form raised portions. The method further includes depositing a hard mask in the trenches and over the upper pad film. The method further includes forming a...


04/05/12 - 20120080732 - Isolation structures for global shutter imager pixel, methods of manufacture and design structures
Pixel sensor cells, e.g., CMOS optical imagers, methods of manufacturing and design structures are provided with isolation structures that prevent carrier drift to diffusion regions. The pixel sensor cell includes a photosensitive region and a gate adjacent to the photosensitive region. The pixel sensor cell further includes a diffusion region...


03/22/12 - 20120068233 - Transistors having stressed channel regions and methods of forming transistors having stressed channel regions
A method of forming a field effect transistor and a field effect transistor. The method includes (a) forming gate stack on a silicon layer of a substrate; (b) forming two or more SiGe filled trenches in the silicon layer on at least one side of the gate stack, adjacent pairs...


03/08/12 - 20120056264 - Method for forming and structure of a recessed source/drain strap for a mugfet
A method and semiconductor structure includes an insulator layer on a substrate, a plurality of parallel fins above the insulator layer, relative to a bottom of the structure. Each of the fins comprises a central semiconductor portion and conductive end portions. At least one conductive strap may be positioned within...


01/26/12 - 20120018812 - Method and structure for balancing power and performance using fluorine and nitrogen doped substrates
Methods and systems evaluate an integrated circuit design for power consumption balance and performance balance, using a computerized device. Based on this process of evaluating the integrated circuit, the methods and systems can identify first sets of integrated circuit transistor structures within the integrated circuit design that need reduced power...


12/29/11 - 20110316084 - Fet with replacement gate structure and method of fabricating the same
A MUGFET and method of manufacturing a MUGFET is shown. The method of manufacturing the MUGFET includes forming temporary spacer gates about a plurality of active regions and depositing a dielectric material over the temporary spacer gates, including between the plurality of active regions. The method further includes etching portions...


11/17/11 - 20110279399 - Interface device with integrated solar cell(s) for power collection
Disclosed herein are embodiments of an interface device (e.g., a display, touchpad, touchscreen display, etc.) with integrated power collection functions. In one embodiment, a solar cell or solar cell array can be located within a substrate at a first surface and an array of interface elements can also be located...


11/17/11 - 20110278649 - Non-uniform gate dielectric charge for pixel sensor cells and methods of manufacturing
A non-uniform gate dielectric charge for pixel sensor cells, e.g., CMOS optical imagers, and methods of manufacturing are provided. The method includes forming a gate dielectric on a substrate. The substrate includes a source/drain region and a photo cell collector region. The method further includes forming a non-uniform fixed charge...


10/06/11 - 20110241220 - Air gaps in a multilayer integrated circuit and method of making same
A multilayer integrated circuit (IC) including a cross pattern of air gaps in a wiring layer and methods of making the multilayer IC are provided. The patterning of the air gaps is independent of the wiring layout. Patterns of air gaps including: parallel alternating stripes of air gaps and dielectric...


09/01/11 - 20110210402 - Metal-gate high-k reference structure
Disclosed are embodiments of an integrated circuit structure that incorporates at least two field effect transistors (FETs) that have the same conductivity type and essentially identical semiconductor bodies (i.e., the same semiconductor material and, thereby the same conduction and valence band energies, the same source, drain, and channel dopant profiles,...


08/25/11 - 20110207298 - Dense pitch bulk finfet process by selective epi and etch
Disclosed is a method of forming a pair of transistors by epitaxially growing a pair of silicon fins on a silicon germanium fin on a bulk wafer. In one embodiment a gate conductor between the fins is isolated from a conductor layer on the bulk wafer so a front gate...


08/11/11 - 20110195349 - Chromeless phase-shifting photomask with undercut rim-shifting element
A phase-shifting photomask with a self aligned undercut rim-shifting element and methods for its manufacture are provided. One embodiment of the invention provides a method of manufacturing a phase-shifting photomask having a self aligned rim-shifting element, the method comprising: applying a patterning film to a first portion of a transparent...


07/28/11 - 20110180862 - Embedded dynamic random access memory device and method
Embodiments of the invention provide an integrated circuit for an embedded dynamic random access memory (eDRAM), a semiconductor-on-insulator (SOI) wafer in which such an integrated circuit may be formed, and a method of forming an eDRAM in such an SOI wafer. One embodiment of the invention provides an integrated circuit...


06/16/11 - 20110140279 - Semiconductor structure incorporating multiple nitride layers to improve thermal dissipation away from a device and a method of forming the structure
Disclosed are embodiments of a semiconductor structure that incorporates multiple nitride layers stacked between the center region of a device and a blanket oxide layer. These nitride layers are more thermally conductive than the blanket oxide layer and, thus provide improved heat dissipation away from the device. Also disclosed are...


06/09/11 - 20110133310 - integrated circuit and a method using integrated process steps to form deep trench isolation structures and deep trench capacitor structures for the integrated circuit
Disclosed is an integrated circuit having at least one deep trench isolation structure and a deep trench capacitor. A method of forming the integrated circuit incorporates a single etch process to simultaneously form first trench(s) and a second trenches for the deep trench isolation structure(s) and a deep trench capacitor,...


05/26/11 - 20110121862 - Circuit with stacked structure and use thereof
An NAND circuit has a stacked structure having at least one symmetric NFET at a bottom of the stack. More particularly, the circuit has a stacked structure which includes an asymmetric FET and a symmetric FET. The symmetric FET is placed at the bottom of the stacked structure closer to...


05/26/11 - 20110121369 - Integrated circuit including finfet rf switch angled relative to planar mosfet and related design structure
An integrated circuit (IC) includes a fin field effect transistor (FinFET) radio frequency (RF) switch; and a planar complementary metal-oxide semiconductor field effect transistor (MOSFET). The planar MOSFET has a channel on a <100> wafer plane and the FinFET RF switch has a channel on a <100> fin plane. The...


05/12/11 - 20110108927 - Damascene gate having protected shorting regions
The present invention relates generally to semiconductor devices and, more specifically, to damascene gates having protected shorting regions and related methods for their manufacture. A first aspect of the invention provides a method of forming a damascene gate with protected shorting regions, the method comprising: forming a damascene gate having:...


05/05/11 - 20110101449 - Asymmetric field effect transistor structure and method
Disclosed are embodiments of an asymmetric field effect transistor structure and a method of forming the structure in which both series resistance in the source region (Rs) and gate to drain capacitance (Cgd) are reduced in order to provide optimal performance (i.e., to provide improved drive current with minimal circuit...


04/07/11 - 20110079828 - Metal gate fet having reduced threshold voltage roll-off
A structure and method to create a metal gate having reduced threshold voltage roll-off. A method includes: forming a gate dielectric material on a substrate; forming a gate electrode material on the gate dielectric material; and altering a first portion of the gate electrode material. The altering causes the first...


03/24/11 - 20110068414 - Integrated circuit device with series-connected fin-type field effect transistors and integrated voltage equalization and method of forming the device
Disclosed is an integrated circuit device having stacked fin-type field effect transistors (FINFETs) with integrated voltage equalization and a method. A multi-layer fin includes a semiconductor layer, an insulator layer above the semiconductor layer and a high resistance conductor layer above the insulator layer. For each FINFET, a gate is...


03/17/11 - 20110062240 - Device and method for providing an integrated circuit with a unique indentification
A device and method for providing an integrated circuit with a unique identification. The device is usable on an integrated circuit (IC) for generating an identification (ID) identifying the IC and includes a plurality of identification cells each utilizing one of a four wire resistor, thin film resistors, and an...


03/10/11 - 20110057258 - Dual stress device and method
A semiconductor device including semiconductor material having a bend and a trench feature formed at the bend, and a gate structure at least partially disposed in the trench feature. A method of fabricating a semiconductor structure including forming a semiconductor material with a trench feature over a layer, forming a...


02/24/11 - 20110042748 - Multi-gate non-planar field effect transistor structure and method of forming the structure using a dopant implant process to tune device drive current
Disclosed are embodiments of a semiconductor structure that includes one or more multi-gate field effect transistors (MUGFETs), each MUGFET having one or more semiconductor fins. In the embodiments, a dopant implant region is incorporated into the upper portion of the channel region of a semiconductor fin in order to selectively...


01/13/11 - 20110006359 - Semiconductor structures and methods of manufacture
Semiconductor structures and methods of manufacture semiconductors are provided which relate to transistors. The method of forming a transistor includes thermally annealing a selectively patterned dopant material formed on a high-k dielectric material to form a high charge density dielectric layer from the high-k dielectric material. The high charge density...


12/30/10 - 20100327360 - Fet with replacement gate structure and method of fabricating the same
A MUGFET and method of manufacturing a MUGFET is shown. The method of manufacturing the MUGFET includes forming temporary spacer gates about a plurality of active regions and depositing a dielectric material over the temporary spacer gates, including between the plurality of active regions. The method further includes etching portions...


12/23/10 - 20100323462 - Process environment variation evaluation
Structures and methods are disclosed for evaluating the effect of a process environment variation. A structure and related method are disclosed including a plurality of electrical structures arranged in a non-collinear fashion for determining a magnitude and direction of a process environment variation in the vicinity of the plurality of...


12/16/10 - 20100314688 - Differential nitride pullback to create differential nfet to pfet divots for improved performance versus leakage
Disclosed are embodiments of an integrated circuit structure with field effect transistors having differing divot features at the isolation region-semiconductor body interfaces so as to provide optimal performance versus stability (i.e., optimal drive current versus leakage current) for logic circuits, analog devices and/or memory devices. Also disclosed are embodiments of...


12/02/10 - 20100301419 - Integrated circuit device with deep trench isolation regions for all inter-well and intra-well isolation and with a shared contact to a junction between adjacent device diffusion regions andan underlying floating well section
Disclosed are embodiments of an improved integrated circuit device structure (e.g., a static random access memory array structure or other integrated circuit device structure incorporating both P-type and N-type devices) and a method of forming the structure that uses DTI regions for all inter-well and intra-well isolation and, thereby provides...


09/16/10 - 20100233873 - Method of forming a semiconductor device using a sacrificial uniform vertical thickness spacer structure
Disclosed is a method of forming planar and non-planar semiconductor devices using a sacrificial gate sidewall spacer with a uniform vertical thickness. The method forms such spacers by selectively growing an epitaxial film on the vertical sidewalls of a gate structure. The use of an epitaxial growth process, as opposed...


09/16/10 - 20100232212 - Split-gate dram with lateral control-gate mugfet
A semiconductor structure of an array of dynamic random access memory cells. The structure includes: a first fin of a first split-gate fin-type field effect transistor (FinFET) device on a substrate; a second fin of a second split-gate fin-type field effect transistor (FinFET) device on the substrate; and a back-gate...


09/16/10 - 20100230779 - Trench generated device structures and design structures for radiofrequency and bicmos integrated circuits
Trench-generated device structures fabricated using a semiconductor-on-insulator (SOI) wafer, design structures embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, as well as methods for fabricating trench-generated device structures. The device structure includes a trench extending through the semiconductor and insulator layers of the SOI...


08/12/10 - 20100200840 - Graphene-based transistor
A graphene layer is formed on a surface of a silicon carbide substrate. A dummy gate structure is formed over the fin, in the trench, or on a portion of the planar graphene layer to implant dopants into source and drain regions. The dummy gate structure is thereafter removed to...


07/08/10 - 20100173500 - Semiconductor wafer structure with balanced reflectance and absorption characteristics for rapid thermal anneal uniformity
Disclosed are embodiments of semiconductor wafer structures and associated methods of forming the structures with balanced reflectance and absorption characteristics. The reflectance and absorption characteristics are balanced by manipulating thin film interferences. Specifically, thin film interferences are manipulated by selectively varying the thicknesses of the different films. Alternatively, reflectance and...


07/01/10 - 20100167504 - Methods of fabricating nanostructures
A method is shown for fabricating nanostructures, and more particularly, to methods of fabricating silicon nanowires. The method of manufacturing a nanowire includes forming a sandwich structure of SiX material and material Si over a substrate and etching the sandwich structure to expose sidewalls of the Si material and the...


07/01/10 - 20100167477 - Localized temperature control during rapid thermal anneal
Disclosed are embodiments of a semiconductor structure and method of forming the structure with selectively adjusted reflectance and absorption characteristics in order to selectively control temperature changes during a rapid thermal anneal and, thereby, to selectively control variations in device performance and/or to selectively optimize the anneal temperature of such...


06/24/10 - 20100155855 - Band edge engineered vt offset device
Band edge engineered Vt offset devices, design structures for band edge engineered Vt offset devices and methods of fabricating such structures is provided herein. The structure includes a first FET having a channel of a first compound semiconductor of first atomic proportions resulting in a first band structure and a...


06/24/10 - 20100155842 - Body contacted hybrid surface semiconductor-on-insulator devices
A portion of a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate is patterned into a semiconductor fin having substantially vertical sidewalls. A portion of a body region of the semiconductor fin is exposed on a top surface of the semiconductor fin between two source regions having a doping of...


05/13/10 - 20100117125 - Semiconductor structures incorporating multiple crystallographic planes and methods for fabrication thereof
A semiconductor structure includes a semiconductor mesa located upon an isolating substrate. The semiconductor mesa includes a first end that includes a first doped region separated from a second end that includes a second doped region by an isolating region interposed therebetween. The first doped region and the second doped...


04/15/10 - 20100090320 - Structure and method for device-specific fill for improved anneal uniformity
Disclosed are embodiments of a wafer that incorporates fill structures with varying configurations to provide uniform reflectance. Uniform reflectance is achieved by distributing across the wafer fill structures having different semiconductor materials such that approximately the same ratio and density between the different semiconductor materials is achieved within each region...


04/08/10 - 20100087037 - Semiconductor device structures with floating body charge storage and methods for forming such semiconductor device structures
Semiconductor device structures including a semiconductor body that is partially depleted to define a floating charge-neutral region supplying a floating body for charge storage and methods for forming such semiconductor device structures. The width of the semiconductor body is modulated so that different sections of the body have different widths....


02/25/10 - 20100044801 - Dual metal gate corner
In view of the foregoing, disclosed herein are embodiments of an improved field effect transistor (FET) structure and a method of forming the structure. The FET structure embodiments each incorporate a unique gate structure. Specifically, this gate structure has a first section above a center portion of the FET channel...


02/18/10 - 20100041225 - Structure, design structure and method of manufacturing dual metal gate vt roll-up structure
A structure, design structure and method of manufacturing is provided for a dual metal gate Vt roll-up structure, e.g., multi-work function metal gate. The method of manufacturing the multi-work function metal gate structure comprises forming a first type of metal with a first work function in a central region and...


02/18/10 - 20100041199 - Field effect transistor with suppressed corner leakage through channel material band-edge modulation, design structure and method
Disclosed are embodiments of field effect transistors (FETs) having suppressed sub-threshold corner leakage, as a function of channel material band-edge modulation. Specifically, the FET channel region is formed with different materials at the edges as compared to the center. Different materials with different band structures and specific locations of those...


02/18/10 - 20100041191 - Split-gate dram with mugfet, design structure, and method of manufacture
A method of manufacturing a dynamic random access memory cell includes: forming a substrate having an insulating region over a conductive region; forming a fin of a fin-type field effect transistor (FinFET) device over the insulating region; forming a storage capacitor at a first end of the fin; and forming...


02/18/10 - 20100039854 - Structure, structure and method of using asymmetric junction engineered sram pass gates
A design structure, structure and method of using and/or manufacturing structures having asymmetric junction engineered SRAM pass gates is provided. The structure includes an SRAM cell having asymmetric junction-engineered SRAM pass gates with a high leakage junction and a low leakage junction. The asymmetric junction-engineered SRAM pass gates are connected...


02/18/10 - 20100039853 - Design structure, structure and method of using asymmetric junction engineered sram pass gates
A design structure, structure and method of using and/or manufacturing structures having asymmetric junction engineered SRAM pass gates is provided. The method includes applying a voltage through asymmetric pull-down nFETs with high junction leakage from their body to their source and low junction leakage from the body to their drain;...


02/18/10 - 20100038728 - Field effect transistor with suppressed corner leakage through channel material band-edge modulation, design structure and method
Disclosed are embodiments of field effect transistors (FETs) having suppressed sub-threshold corner leakage, as a function of channel material band-edge modulation. Specifically, the FET channel region is formed with different materials at the edges as compared to the center. Different materials with different band structures and specific locations of those...


02/18/10 - 20100038720 - Structure, design structure and method of manufacturing dual metal gate vt roll-up structure
A structure, design structure and method of manufacturing is provided for a dual metal gate Vt roll-up structure, e.g., multi-work function metal gate. The multi-work function metal gate structure comprises a first type of metal with a first work function in a central region and a second type of metal...


02/18/10 - 20100038694 - Split-gate dram with mugfet, design structure, and method of manufacture
A semiconductor structure for a dynamic random access memory cell, the structure including: a fin of a fin-type field effect transistor (FinFET) device formed over and spaced apart from a conductive region of a substrate; a storage capacitor connected to a first end of the fin; and a back-gate at...


02/04/10 - 20100031223 - Systems for real-time contamination, environmental, or physical monitoring of a photomask
Systems for real-time contamination, environmental, or physical monitoring of a photomask. The system includes an electronics package physically mounted to the photomask and a processing device in communication with the electronics package. The electronics package includes a sensor configured to monitor the attribute and generate sensor data. The processing device...


02/04/10 - 20100029021 - Methods for real-time contamination, environmental, or physical monitoring of a photomask
Methods for real-time contamination, environmental, or physical monitoring of a photomask. An attribute of a photomask is monitored using a sensor of an electronics package attached to the photomask. The methods further include generating one or more sensor signals relating to the monitored attribute with the sensor and transmitting the...


01/14/10 - 20100006823 - Semiconducting device having graphene channel
The present invention, in one embodiment, provides a semiconductor device including a substrate having an dielectric layer; at least one graphene layer overlying the dielectric layer; a back gate structure underlying the at least one graphene layer; and a semiconductor-containing layer present on the at least one graphene layer, the...


12/24/09 - 20090319973 - Spacer fill structure, method and design structure for reducing device variation
A design structure is provided for spacer fill structures and, more particularly, spacer fill structures, a method of manufacturing and a design structure for reducing device variation is provided. The structure includes a plurality of dummy fill shapes in different areas of a device which are configured such that gate...


12/10/09 - 20090305470 - Isolating back gates of fully depleted soi devices
Methods, structure and design structure having isolated back gates for fully depleted semiconductor-on-insulator (FDSOI) devices are presented. In one embodiment, a method may include providing a FDSOI substrate having a SOI layer over a buried insulator over a first polarity-type substrate, the first polarity-type substrate including a second polarity-type well...


12/10/09 - 20090302402 - Mugfet with stub source and drain regions
The present invention provides a semiconductor device that includes at least one semiconductor Fin structure atop the surface of a substrate; the semiconducting fin structure including a channel of a first conductivity type and source/drain regions of a second conductivity type, the source/drain regions present at each end of the...


12/10/09 - 20090302374 - Differential nitride pullback to create differential nfet to pfet divots for improved performance versus leakage
Disclosed are embodiments of an integrated circuit structure with field effect transistors having differing divot features at the isolation region-semiconductor body interfaces so as to provide optimal performance versus stability (i.e., optimal drive current versus leakage current) for logic circuits, analog devices and/or memory devices. Also disclosed are embodiments of...


12/10/09 - 20090302366 - Structure and design structure having isolated back gates for fully depleted soi devices
Methods, structure and design structure having isolated back gates for fully depleted semiconductor-on-insulator (FDSOI) devices are presented. In one embodiment, a method may include providing a FDSOI substrate having a SOI layer over a buried insulator over a first polarity-type substrate, the first polarity-type substrate including a second polarity-type well...


12/03/09 - 20090298220 - Imagers having electrically active optical elements
A method of fabricating a CMOS image sensor comprising an array of active pixel cells. Each active pixel cell includes a substrate; a photosensing device formed at or below a substrate surface for collecting charge carriers in response to incident light; and, one or more light transmissive conductive wire structures...


10/01/09 - 20090244501 - Apparatus for real-time contamination, environmental, or physical monitoring of a photomask
An apparatus for real-time contamination, environmental, or physical monitoring of a photomask. The apparatus includes a photomask having a patterned region configured to correspond to features of an integrated circuit and a sensor physically coupled with the photomask. The sensor is configured to monitor an attribute related to the photomask....


10/01/09 - 20090243029 - Method, structure and design structure for customizing history effects of soi circuits
A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a structure which comprises a high-leakage dielectric formed in a divot on each side of a segmented FET comprised of active silicon islands and gate electrodes thereon, and a...


10/01/09 - 20090243000 - Method, structure and design structure for customizing history effects of soi circuits
A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a high-leakage dielectric formed over an active region of a FET and a low-leakage dielectric formed on the active region and adjacent the high-leakage dielectric. The low-leakage dielectric has...


10/01/09 - 20090242985 - Method, structure and design structure for customizing history effects of soi circuits
A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a high-leakage dielectric formed between a gate electrode and an outer portion of an active region of a FET. Also provided is a structure having a high-leakage dielectric formed...


09/24/09 - 20090236632 - Fet having high-k, vt modifying channel and gate extension devoid of high-k and/or vt modifying material, and design structure
A field effect transistor (FET) including a high dielectric constant (high-k), threshold voltage (Vt) modifying channel and a gate extension devoid of the high-k and/or Vt modifying material, and a related design structure, are disclosed. In one embodiment, a FET may include a gate having a channel region thereunder including...


09/10/09 - 20090227077 - Low-capacitance contact for long gate-length devices with small contacted pitch
Disclosed are planar and non-planar field effect transistor (FET) structures and methods of forming the structures. The structures comprise segmented active devices (e.g., multiple semiconductor fins for a non-planar transistor or multiple semiconductor layer sections for a planar transistor) connected at opposite ends to source/drain bridges. A gate electrode is...


08/20/09 - 20090206407 - Semiconductor devices having tensile and/or compressive stress and methods of manufacturing
A semiconductor device and method of manufacturing is disclosed which has a tensile and/or compressive strain applied thereto. The method includes forming at least one trench in a material; and filling the at least one trench by an oxidation process thereby forming a strain concentration in a channel of a...


08/06/09 - 20090197382 - Multi-gated, high-mobility, density improved devices
Disclosed herein are embodiments of an improved method of forming p-type and n-type MUGFETs with high mobility crystalline planes in high-density, chevron-patterned, CMOS devices. Specifically, semiconductor fins are formed in a chevron layout oriented along the centerline of a wafer. Gates are formed adjacent to the semiconductor fins such that...


07/30/09 - 20090189223 - Complementary metal gate dense interconnect and method of manufacturing
Complementary metal gate dense interconnects and methods of manufacturing the interconnects is provided. The method comprises forming a first metal gate on a wafer and second metal gate on the wafer. A conductive interconnect material is deposited in a space formed between the first metal gate and the second metal...


06/18/09 - 20090158231 - Design structure for a redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same
A design structure for an integrated circuit including a first wire of a first level of wiring tracks, a second wire of a second level of wiring tracks, a third wire of a third level of wiring tracks, and a fourth wire located a first distance from the second wire...


05/14/09 - 20090121291 - Dense chevron non-planar field effect transistors and method
Disclosed are embodiments of semiconductor structure and a method of forming the semiconductor structure that simultaneously maximizes device density and avoids contacted-gate pitch and fin pitch mismatch, when multiple parallel angled fins are formed within a limited area on a substrate and then traversed by multiple parallel gates (e.g., in...


05/07/09 - 20090119626 - Design structure including transistor having gate and body in direct self-aligned contact
A design structure including a transistor having a directly contacting gate and body is disclosed. In one embodiment, the transistor includes a gate; a body; and a dielectric layer extending over the body to insulate the gate from the body along an entire surface of the body except along a...


04/30/09 - 20090111225 - Cmos structure and method including multiple crystallographic planes
A complementary metal oxide semiconductor (CMOS) structure includes a semiconductor substrate having first mesa having a first ratio of channel effective horizontal surface area to channel effective vertical surface area. The CMOS structure also includes a second mesa having a second ratio of the same surface areas that is greater...


04/23/09 - 20090102505 - Remotely configurable chip and associated method
A chip is provided that includes a plurality of on-chip configurable features having a disabled and an enabled state. The on-chip configurable features are each operable to change from the disabled state to the enabled state upon receipt of a valid enablement configuration from an enabling entity. A method for...


04/23/09 - 20090101978 - Fin-type field effect transistor structure with merged source/drain silicide and method of forming the structure
Disclosed herein are embodiments of a design structure of a multiple fin fin-type field effect transistor (i.e., a multiple fin dual-gate or tri-gate field effect transistor) in which the multiple fins are partially or completely merged by a highly conductive material (e.g., a metal silicide). Merging the fins in this...


04/16/09 - 20090096066 - Structure and method for device-specific fill for improved anneal uniformity
Disclosed is a design structure embodiment of a wafer that incorporates fill structures with varying configurations to provide uniform reflectance. Uniform reflectance is achieved by distributing across the wafer fill structures having different semiconductor materials such that approximately the same ratio and density between the different semiconductor materials is achieved...


03/26/09 - 20090078999 - Semiconductor device structures with floating body charge storage and methods for forming such semiconductor device structures.
Semiconductor device structures including a semiconductor body that is partially depleted to define a floating charge-neutral region supplying a floating body for charge storage and methods for forming such semiconductor device structures. The width of the semiconductor body is modulated so that different sections of the body have different widths....


03/12/09 - 20090065834 - Imagers having electrically active optical elements
A CMOS image sensor comprising an array of active pixel cells. Each active pixel cell includes a substrate; a photosensing device formed at or below a substrate surface for collecting charge carriers in response to incident light; and, one or more light transmissive conductive wire structures formed above the photosensing...


03/12/09 - 20090065818 - Structure for imagers having electrically active optical elements
A design structure embodied in a machine readable medium for use in a design process, the design structure representing a CMOS image sensor device comprising an array of active pixel cells. Each active pixel cell includes a substrate; a photosensing device formed at or below a substrate surface for collecting...


International Business Machines Corporation

Archived*
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20130001693 - Band edge engineered vt offset device


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