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11/08/07 - USPTO Class 365 |  92 views | #20070258286 | Prev - Next | About this Page  365 rss/xml feed  monitor keywords

Boosting methods for nand flash memory

USPTO Application #: 20070258286
Title: Boosting methods for nand flash memory
Abstract: A floating gate memory array includes row control circuits that provide a programming voltage to a selected word line and provide a stair-like pattern of boosting voltages to unselected word lines. Boosting voltages descend with increased distance from the selected word line. Boosting voltages are increased in small increments up to their final values. (end of abstract)



Agent: Winston & Strawn, LLP - Washington, DC, US
Inventor: Masaaki Higashitani
USPTO Applicaton #: 20070258286 - Class: 365185140 (USPTO)

Boosting methods for nand flash memory description/claims


The Patent Description & Claims data below is from USPTO Patent Application 20070258286, Boosting methods for nand flash memory.

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Previous Patent Application:
Non-volatile memory
Next Patent Application:
Flash programmer for programming nand flash and nor/nand combined flash
Industry Class:
Static information storage and retrieval

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