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  Bit line of a semiconductor device and method for fabricating the sameRelated Patent Categories: Semiconductor Device Manufacturing: Process, Making Field Effect Device Having Pair Of Active Regions Separated By Gate Structure By Formation Or Alteration Of Semiconductive Active Regions, Having Insulated Gate (e.g., Igfet, Misfet, Mosfet, Etc.), Having Additional Gate Electrode Surrounded By Dielectric (i.e., Floating Gate), Including Elongated Source Or Drain Region Disposed Under Thick Oxide Regions (e.g., Buried Or Diffused Bitline, Etc.)The Patent Description & Claims data below is from USPTO Patent Application 20060292801. Brief Patent Description - Full Patent Description - Patent Application Claims
BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to a method for fabricating a semiconductor device, and more particularly to a method for fabricating a bit line of a semiconductor device. [0003] 2. Description of the Related Art [0004] Generally, in memory cells of semiconductor devices, a bit line is known as a signal-transmission passage between components constituting unit memory devices which can store 1-bit unit data. [0005] FIG. 1 illustrates a bit line formed by a method for fabricating a bit line of a semiconductor device in accordance with conventional methods. [0006] Referring to FIG. 1, in fabricating the bit line of a semiconductor device, a first interlayer dielectric film 110 is formed on a semiconductor substrate 100 having gates (not shown) and landing plugs (not shown) formed thereon. Next, a portion of the first interlayer dielectric film 110 is etched such that the upper parts of the landing plugs are exposed, thereby forming a bit line contact hole (not shown). A barrier metal film (not shown) is formed inside the bit line contact hole. Next, a conductive material (not shown) is formed such that the bit line contact hole is embedded, thereby forming a bit line contact (not shown). Next, a bit line-forming material (not shown), e.g., tungsten and nitride material, is deposited on the bit line contact and first interlayer dielectric film 110. [0007] The bit line-forming material is then etched to overlap with the bit line contact, thereby forming bit line stacks 120 in which, for example, tungsten 125 and a hard mask nitride film 127 are sequentially stacked. Next, bit line spacers 130 are formed on the sidewalls of the bit line stacks 120. The bit line spacers 130 may be formed from a nitride film, which has high tensile stress. Then, an oxide film (not shown), which is a second interlayer dielectric film, is formed on the first interlayer dielectric film 110, via a high density plasma (HDP) process, such that the gap between the bit line stacks 120 is embedded. The oxide film, formed by the high density plasma (HDP) process, has compression stress. [0008] The bit line of the semiconductor device in accordance with conventional methods suffer from collapse of the bit line stacks 120 due to different properties between the bit line spacer 130 and the oxide film in the course of embedding the oxide film, as the second interlayer dielectric film, during a high density plasma (HDP) process. Bit line spacers 130 exhibit high tensile stress, while the oxide film, as the second interlayer dielectric film, exhibits compression stress. The different types of stress results in a collapse of the bit line stacks 120, as represented by `A` in FIG. 1. [0009] Such stress-induced collapse of the bit line stacks 120 becomes more severe as the semiconductor device is highly integrated. For example, a conventional 80 nm-sized semiconductor device can resist stress with the second interlayer dielectric film by securing a final critical dimension of about 70 nm of the bit line stacks 120. As the dimensions of semiconductor devices have recently been reduced to 65 nm due to high degree of integration thereof, a final critical dimension of the bit line stacks is sharply decreased to 30 nm. Consequently, capability of the bit line stacks to withstand stress with the second interlayer dielectric film is lowered, thereby resulting in a collapse thereof, which in turn leads to a short-circuit with adjacent bit line stacks, thus deteriorating characteristics of the devices. As such, it is difficult to fabricate high-reliability devices. SUMMARY OF THE INVENTION [0010] Embodiments of the present invention alleviate stress between the bit line stack and the second interlayer dielectric film for insulating bit line stacks. [0011] In accordance with an aspect of the present invention, a bit line of a semiconductor device comprises a first interlayer dielectric film disposed on a semiconductor substrate; a plurality of bit line stacks disposed on the first interlayer dielectric film; bit line spacers disposed on side walls of the bit line stacks; and a buffer film disposed on the bit line spacers, the first interlayer dielectric film, and the bit line stacks. The bit line stacks may be made of a tungsten film and a hard mask nitride film sequentially stacked. The bit line spacers may be made of a nitride film. [0012] In accordance with another aspect of the present invention, a method for fabricating a bit line of a semiconductor device comprises forming bit line stacks on a first interlayer dielectric film formed on a semiconductor substrate; forming bit line spacers on side walls of the bit line stacks; forming a buffer film on the first interlayer dielectric film and the bit line stacks; annealing the buffer film to lower tensile stress thereof; and forming a second interlayer dielectric film on an entire surface of the resulting structure having the buffer film formed thereon. The bit line stack-forming material may be made of a tungsten film and a hard mask nitride film sequentially stacked. The bit line spacers may be formed of a nitride film. The buffer film may be formed of an oxide film, via atomic layer deposition (ALD) utilizing pyridine as a catalyst. [0013] In one embodiment of the present invention, annealing can be carried out at a temperature of about 650.degree. C. to 700.degree. C. for about 120 seconds under nitrogen atmosphere. BRIEF DESCRIPTION OF THE DRAWINGS [0014] Embodiments of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: [0015] FIG. 1 illustrates a bit line formed by a method for fabricating a bit line of a semiconductor device in accordance with conventional methods; and [0016] FIGS. 2 through 4 are cross-sectional views illustrating bit line of a semiconductor device in accordance with an embodiment of the present invention. DESCRIPTION OF THE EMBODIMENTS [0017] Embodiments of the present invention will be described in more detail with reference to accompanying drawings, such that those skilled in the art can easily practice the present invention. In the drawings, thicknesses of various layers and regions are exaggerated for clarity. Like numbers refer to like elements throughout the specification and drawings. [0018] FIGS. 2 through 4 are cross-sectional views illustrating a bit line of a semiconductor device in accordance with an embodiment of the present invention. [0019] FIG. 4 is a cross-sectional view showing the structure of bit line of a semiconductor device in accordance with an embodiment of the present invention. Referring to FIG. 4, a first interlayer dielectric film 210 is disposed on a semiconductor substrate 200 and a plurality of bit line stacks 220 are disposed on the first interlayer dielectric film 210. A plurality of bit line stacks 220 may have a structure in which a tungsten film 225 and a hard mask nitride film 227 are sequentially stacked. Bit line spacers 230 are disposed on side walls of the bit line stacks 220. Bit line spacers 230 are made from nitride films. A buffer film 240 is disposed on bit line spacers 230, first interlayer dielectric film 210, and bit line stacks 220. The buffer film 240 is made from an oxide film. [0020] In such a structure, the buffer film 240 serves to alleviate stress between the bit line spacers 230 and a second interlayer dielectric film (not shown) which will be formed on the buffer film 240 via a subsequent process, preventing a collapse of the bit line stacks 220 due to such stress. Continue reading... Full patent description for Bit line of a semiconductor device and method for fabricating the same Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Bit line of a semiconductor device and method for fabricating the same patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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