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  Bist to provide jitter data and associated methods of operationUSPTO Application #: 20060290398Title: Bist to provide jitter data and associated methods of operation Abstract: In an embodiment, a transmitter circuit is in an integrated circuit die with a test latch, and the test latch is enabled by a test clock signal to under-sample the transmit signal from the transmitter circuit. In a method of operation, a transmit signal is generated in an integrated circuit die, and the transmit signal is under-sampled in a test latch in the integrated circuit triggered by a test clock signal. Output data from the test latch is transmitted to a test device that is separated from the integrated circuit die. (end of abstract) Agent: Schwegman, Lundberg, Woessner & Kluth, P.A. - Minneapolis, MN, US Inventors: Ofir Kanter, Eran Peleg USPTO Applicaton #: 20060290398 - Class: 327163000 (USPTO) The Patent Description & Claims data below is from USPTO Patent Application 20060290398. Brief Patent Description - Full Patent Description - Patent Application Claims
TECHNICAL FIELD [0001] This application relates generally to testing of integrated circuits and, more particularly, to a Built-In Self-Tester (BIST) to provide jitter data and associated methods of operation. BACKGROUND [0002] Jitter is a deviation or displacement of pulses in a high-frequency digital or analog signal. As the name suggests, jitter can be thought of as shaky pulses. Jitter is the variation of an event from its ideal position in time. Among the causes of jitter are electromagnetic interference and crosstalk with other signals. Jitter can cause a display monitor to flicker, affect the ability of the processor in a personal computer to perform as intended, introduce clicks or other undesired effects to audio signals, and cause the loss of data transmitted between network devices. [0003] Measuring transmitter jitter of high speed input/outputs (I/Os) is one of the most complicated production tests. The complexity is due to the ambiguous ways to measure the jitter, the high frequency of the transmitted signal and the external dedicated instrument that gets the signal, post processes it, and provides an output as its' jitter. Yet, the importance of this parameter is critical, since according to the jitter value, the robustness of the transmitted signal is tested, and one concludes the chip's performance on real (customer) systems according to the jitter value. In one way to measure the jitter of a signal, one samples it in high frequencies, and via post processing, estimates a difference between the actual transitions and the theoretical transitions. The higher the signal's frequency is--the test becomes more important and difficult to implement, and the instrument that measures the jitter becomes more complex and expensive. Traditionally, signal frequencies rise over time, therefore the challenge is growing. [0004] In conservative ways, transmit jitter is measured by a unique ad hoc external instrument attached to a tester. [0005] There is a need for improved circuits and methods for testing integrated circuits for jitter. BRIEF DESCRIPTION OF THE DRAWINGS [0006] FIG. 1 is a block diagram of an integrated circuit die and a test device according to various embodiments; [0007] FIG. 2A-2C is a plot of an under-sampling method according to various embodiments; [0008] FIG. 3A-3C is a plot of a jittered signal; [0009] FIG. 4 is a plot of multiple samples of a jittered signal according to various embodiments; [0010] FIG. 5 is a plot of a Gaussian distribution according to various embodiments; [0011] FIG. 6 is a flow diagram of several methods according to various embodiments; and [0012] FIG. 7 is a block diagram of a system according to various embodiments. DETAILED DESCRIPTION [0013] In the following detailed description of various embodiments, reference is made to the accompanying drawings that form a part hereof, and in which are shown by way of illustration, and not of limitation, specific embodiments in which the subject matter may be practiced. In the drawings, like numerals describe substantially similar components throughout the several views. The embodiments illustrated are described in sufficient detail to enable those skilled in the art to practice the teachings disclosed herein. Other embodiments may be utilized and derived therefrom, such that compositional, structural, and logical substitutions and changes may be made without departing from the scope of this disclosure. The following detailed description, therefore, is not to be taken in a limiting sense. Examples and embodiments merely typify possible variations. Individual components and functions are optional unless explicitly required, and the sequence of operations may vary. Portions and features of some embodiments may be included in or substituted for those of others. The following description is, therefore, not to be taken in a limiting sense. [0014] According to various embodiments, an internal feature is added to the silicon of an integrated circuit chip that provides the main jitter components of high frequency transmit signals, externally based on a clean and low frequency reference clock signal driven from a tester. In particular, a precise latch is internal in the silicon that receives a transmit signal as an input and a low frequency precise clock (latch enable) from the tester. The transmit signal is to be measured for jitter. According to various embodiments, the transmit signal is under-sampled. Using the under-sampling method of the embodiments, the clock's frequency is low, and a simple tester can provide the clock. A latch output is transferred to the tester and then sampled into the tester's memory. [0015] After the under-sampling is over, and enough information resides in the memory, post processing provides differences between the signal's actual transitions and theoretical transitions. The more data that is collected, the more information on jitter components can be provided, and test time is balanced against the accuracy of the results to determine how much data is collected. [0016] FIG. 1 is a block diagram of an integrated circuit die 100 and a test device 110 according to various embodiments. The die 100 is a silicon chip, and elements of an integrated circuit are formed on the silicon chip. The test device 110 is separated from the integrated circuit die 100, and is not part of the same silicon chip. [0017] A Phase Locked Loop (PLL) 120 is located on the die 100, and is coupled to a transmitter circuit 130 to provide a timing reference signal 125. The transmitter circuit 130 generates a high frequency transmit signal 135 based on the timing reference signal 125. The transmit signal 135 is coupled to a transmit signal input 138 of a test latch 140. The transmitter circuit 130 and the test latch 140 are also located on the die 100. The test latch 140 is coupled to receive a low frequency test clock signal 145 at a clock input 148. The test latch 140 is triggered or enabled by the test clock signal 145 to sample the transmit signal 135. [0018] The test clock signal 145 is generated by the test device 110 and coupled to the die 100 including the test latch 140. [0019] The test latch 140 transmits output data 155 through a data output 158 to the test device 110. The output data 155 includes samples of the transmit signal 135 sampled by the test latch 140. The output data 155 is stored in a memory 170 in the test device 110. The memory 170 is a Flash memory or a random access memory (RAM) or a disk drive storage device or any other type of appropriate memory. [0020] Design for testability (DFT) features are included in an integrated circuit to provide for embedded testing of certain integrated circuit functions. A Built-In Self-Tester (BIST) is a DFT feature. The test latch 140 according to various embodiments is such a BIST. Continue reading... Full patent description for Bist to provide jitter data and associated methods of operation Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Bist to provide jitter data and associated methods of operation patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Bist to provide jitter data and associated methods of operation or other areas of interest. ### Previous Patent Application: Method and apparatus for glitch-free control of a delay-locked loop in a network device Next Patent Application: Capacitor pulse forming network with multiple pulse inductors Industry Class: Miscellaneous active electrical nonlinear devices, circuits, and systems ### FreshPatents.com Support Thank you for viewing the Bist to provide jitter data and associated methods of operation patent info. IP-related news and info Results in 0.54791 seconds Other interesting Feshpatents.com categories: Accenture , Agouron Pharmaceuticals , Amgen , AT&T , Bausch & Lomb , Callaway Golf |
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